An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process receiving injections. Further, the quadrature outputs from the 4-phase signals from the RO are edge-combined using an XOR gate to produce differential outputs with twice the RO frequency as shown in Fig. 7.9.2.

📋 论文概要

本文提出了一种在65nm CMOS工艺下实现的8位6-12GHz DC调制斜坡式相位插值器，功耗为0.18mW/GHz。通过使用差分输入时钟生成电容电流产生斜坡信号，并采用内部复制偏置环路稳定DC电平，同时结合带开关电容负载的V-to-I电路跟踪PVT变化，解决了斜坡线性度和工艺鲁棒性问题。

💡 主要创新点

• 提出DC调制斜坡技术，通过内部复制偏置环路精确控制斜坡信号的DC电平，提高线性度。
• 采用带开关电容负载的V-to-I电路生成偏置电流，使积分电流跟踪工艺、电压、温度（PVT）变化，确保斜坡线性度。
• 引入虚拟开关设计，有效减少时钟馈通效应，提升相位插值精度。

🏷 关键词

📄 原文摘要

capacitor current based on the differential input clocks to generate differential ramp signals. The internal loop within the replica bias sets the DC level of the ramp signal. To ensure the ramp’s linearity across process corners, a V-to-I with switched cap load (CL, using the same type of capacitor as C) is employed to generate bias current (IBIAS) for the ramp generator. IBIAS is directly proportional to CL ensuring that the integrating current (IINT) tracks variation in the capacitor (C) across PVT. Additionally, the inclusion of dummy switches in the design helps mitigate clock feedthrough at high frequency, preserving ramp linearity. A VTH tracking circuit is introduced to ensure that the inverter’s VTH remains at VDD/2 across PVT variations in the inverter-based comparator (Fig. 7.9.3). This circuit employs a feedback loop utilizing an op-amp to precisely control the current flowing through the PMOS and NMOS transistor to set the inverter output at VDD/2 for

👥 作者与机构

Soumen Mohapatra, Emad Afshar, Zhiyuan Zhou, Deukhyoun Heo, Figure 7.9.3 shows a detailed circuit diagram of the ramp generator, which integrates