A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology

📋 论文概要

本文提出一款采用3抽头前馈均衡（FFE）和18抽头判决反馈均衡（DFE）的112Gb/s串行链路收发器，支持高达43dB插入损耗的信道，采用7nm FinFET工艺实现。该设计通过模拟均衡器替代传统ADC/DSP架构，在满足高速率传输的同时降低功耗。

💡 主要创新点

• 采用3-tap FFE和18-tap DFE的模拟接收机架构，避免了高功耗的ADC/DSP方案，实现112Gb/s PAM-4信号在43dB损耗信道下的可靠接收。
• 在7nm FinFET工艺下优化了均衡器电路，支持高达43dB的插入损耗补偿，满足数据中心和城域网对高带宽的需求。

🏷 关键词

📄 原文摘要

Lakshmi Rao1, Karapet Khanoyan1, Hamid Hatamkhani1, Xiaochen Yang1, Xin Meng1, Alexander Wong2, Jun Kim2, Ping Jing2, Yehui Sun2, Ali Nazemi1, Dean Liu2, Anthony Brewster1, Jun Cao1, Afshin Momtaz1 Broadcom, Irvine, CA Broadcom, San Jose, CA 1 2 Social media, video streaming and working at home fuels the demand for bandwidth in metro networks and data centers and pushes serial link data rates into 100Gb/s territory. To cope with severe channel impairments at 112Gb/s PAM-4 with >30dB loss at Nyquist, recently published transceivers [1-4] adopted ADC/DSP-based receivers in advanced FinFET processes. This work presents a low-power and area-efficient non-ADC/DSPbased transceiver that employs fully adaptive 3-tap FFE/18-tap DFE at the receiver (RX) and a 7b DAC-based transmitter (TX) up to 112Gb/s in 7nm FinFET technology for largescale ASIC applications. The transceiver block diagram is illustrated in Fig. 6.1.1. The RX input signal goes to the

👥 作者与机构

Bo Zhang1, Anand Vasani1, Ashutosh Sinha2, Alireza Nilchi1, Haitao Tong1,