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本文提出了一种224Gb/s PAM-4 SerDes接收器，实现了31dB损耗补偿和1.41pJ/b的能效，满足数据中心对高带宽、低功耗电接口的需求。
Itamar Levin1, Ari Gordon1, Yaniv Sabag1, Vitali Rahinski1, Gadi Ori1, Noam Familia1, Stas Litski1, Tali Warshavsky1, Udi Virobnik1, Yeshayahu Horwitz1, Ajay Balankutty2, Shiva Kiran2, Samuel Palermo3, Peng Mike Li4, Ariel Cohen1 Intel, Jerusalem, Israel; 2Intel, Hillsboro, OR Texas A&M University, College Station, TX; 4Intel, San Jose, CA 1 3 The emergence of cloud computing, machine learning, and artificial intelligence is gradually saturating network workloads, necessitating rapid growth in datacenter bandwidth, which approximately doubles every 3-4 years. New electrical interfaces that demand dramatic increases in SerDes transceiver speed are being developed to support this. This paper presents a power-efficient 224Gb/s-PAM-4 ADC-based receiver in a 5nm CMOS process that targets next generation Ethernet for chip-to-module applications, envisioned to be the first use-case scenario at this data-rate. Doubling the data-rate from
Yoav Segal1, Amir Laufer1, Ahmad Khairi1, Yoel Krupnik1, Marco Cusmai1,