JSSC Wireline I/O — ISSCC & JSSC 知识库

JSSC 2024第1期Wireline I/O

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ

4纳米工艺HBM3接口，采用电阻调谐偏移校准和原位余量检测技术，实现9.0 Gb/s/pin高速访问。

4nm FinFET, 0.66/0.30V, 9.0 Gb/s/pin, 0.29 pJ/bit

JSSC 2024第5期Wireline I/OPAM-4

Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS

28nm CMOS工艺下设计的非相干100Gbps双波段PAM-4塑料光纤链路

28nm CMOS, 100Gb/s@3m, 574mW, BER<2.2e-4

JSSC 2024第7期Wireline I/O

A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method Jonghyun Kim and

一款基于StrongARM锁存比较器和平方取中法的10Gb/s全数字真随机数生成器

28nm CMOS, 10Gb/s吞吐量, 0.121pJ/bit能效

JSSC 2024第10期Wireline I/O

VI. C ONCLUSION This article demonstrates a hybrid-integrated 112-Gb/s SiPh O-TRX for LD CPO. To achieve high-speed performance while optimizing power consumption, a 180-nm CMOS SOI MZM and Ge PD are proposed. The integration of these SiPh devices enables a compact form factor and reliable performance. The O-TRX also consists of the four-channel driver and TIA developed on a 180-nm SiGe BiCMOS process. The driver uses a custom-designed second-order AFB CTLE and Ind. PEQ to compensate for channel losses up to 12 dB.

本文展示了一种混合集成的112Gb/s硅光子光收发器，优化功耗并实现紧凑可靠性能。

112Gb/s, 10dB通道损耗

JSSC 2023第1期Wireline I/OFlash Memory

A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface Jong Hak Y uh , Y en-Lung Jason Li, Heguang Li, Y oshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Y eong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Y ap, Demin Wang, Steve Kim, Y onggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu , Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen , Indra K. V ., V . S. N. K. Chaitanya G., V enky Ramachandra, Y osuke Kato, Ravi J. Kumar, Huijuan Wang, Farookh Moogat, In-Soo Y oon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Y anagidaira, Takuyo Kodama, Ryo Fukuda

1Tb 4位/单元162层3D闪存，采用中央阶梯结构和CTW架构，实现15Gb/mm²面密度和60MB/s编程吞吐量。

15Gb/mm²面密度，60MB/s编程吞吐量，65µs最佳tR，2.4Gb/s IO速度

JSSC 2023第1期Wireline I/ODRAM

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based

介绍了一种192-Gb 896-GB/s的HBM3 DRAM，采用低功耗高可靠性设计。

192-Gb 896-GB/s 1.0-V

JSSC 2023第1期Wireline I/ODRAM

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and V arious Activation Functions for Deep Learning Application Daehan Kwon

提出基于GDDR6的1.25V 8Gb 16Gbps内存加速器，支持深度学习操作并优化性能。

1.25V, 8Gb, 16Gbps/pin, 1TFLOPS

JSSC 2023第4期Wireline I/ODRAM

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features Yesin Ryu , Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim , Hyochang Kim , Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong , Sunghwan Joo , Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim , Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn , Sang-Joon Hwang, and

本文提出了一种16GB HBM3 DRAM设计，通过源同步总线和片上纠错技术实现1024 GB/s带宽。

16GB容量，1024 GB/s带宽，8 Gb/s/pin，105°C高温稳定运行

JSSC 2023第4期Wireline I/O

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS

Intel 4 CMOS工艺下7Gbps抗侧信道攻击的乘法掩码AES引擎

7Gbps, 65%面积开销, 4%性能开销

JSSC 2023第9期Wireline I/O

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

提出一种基于SPAD的量子随机数生成器，采用量子随机触发器方法，并通过建模和补偿熵降级实现高效随机数生成。

3.3 Gb/s

JSSC 2023第9期Wireline I/OOptical I/O

New Associate Editor I

Samuel Palermo教授成为IEEE JSSC期刊的新任副主编，专注于高速SerDes电路和硅光子互连技术。

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JSSC 2023第11期Wireline I/O

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s Ji-Young Kim

提出一种低功耗TSV I/O设计，用于HBM，数据速率达10Gb/s。

65nm CMOS, 0.179–0.185 pJ/b/pF, 5–10 Gb/s

JSSC 2022第1期Wireline I/OEqualizerPAM-4

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET

本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。

112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b

JSSC 2022第1期Wireline I/OPAM-4DRAM

An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido

通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。

22 Gbps per-pin data rate

JSSC 2022第1期Wireline I/O

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

2021年IEEE ISSCC精选论文特辑，涵盖有线、数字电路、机器学习等多个领域的前沿研究。

224-Gb/s, 200-Gb/s, 112-Gb/s

JSSC 2022第5期Wireline I/OPAM-4Neural Network Accelerator

A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS

22nm FinFET CMOS工艺下实现的高能效128Gb/s单端PAM4线性TIA

22nm FinFET CMOS, 0.8V, 128Gb/s PAM4, 59.3dBΩ增益, 11.2mW功耗, 45.5GHz带宽, 27μArms输入噪声

JSSC 2022第6期Wireline I/OEmerging MemoryNeural Network Accelerator

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device Y en-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang

22纳米1Mb 1024位读取数据保护的STT-MRAM宏，采用近存移位旋转功能降低峰值电流和能耗。

42.67 GB/s读取带宽，0.23 pJ/bit能效

JSSC 2021第1期Wireline I/O

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

2020年IEEE国际固态电路会议精选论文特刊，涵盖高速互连、数字电路及AI等领域。

112 Gb/s PAM-4, BER <1E-8, 37-dB插入损耗

JSSC 2021第4期Wireline I/OFlash Memory

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage Daehoon Na , Jang-woo Lee, Seon-Kyoo Lee, Hwasuk Cho, Junha Lee, Manjae Y ang, Eunjin Song, Anil Kavala, Tongsung Kim, Dong-Su Jang, Y oungmin Jo, Ji-Y eon Shin, Byung-Kwan Chun, Tae-sung Lee, Byunghoon Jeong, Chi-Weon Y oon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae Seok Byeon, Jinyub Lee, and Jai

本文提出了一种1.2V、1.8Gb/s/pin的16Tb NAND闪存多芯片封装方案，采用第三代F-chip提升性能。

1.2V, 1.8Gb/s/pin, 16Tb

JSSC 2021第8期Wireline I/OEqualizerDRAM

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer Hyeongjun Ko , Mino Kim

提出一种用于高容量DRAM的控制器PHY，采用阻尼电阻辅助脉冲前馈均衡器减少信号干扰。

1067 Mb/s时C/A信号时序裕量从0.23 UI提升至0.29 UI，2133 Mb/s时DQ信号读写时序裕量分别为0.53 UI和0.72 UI

JSSC 2020第3期Wireline I/OEqualizer

An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication—Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit Yusang Chun , Student Member , IEEE

提出一种无需均衡器的ISI弹性Dicode编码方案，用于低带宽有线通信。

65-nm CMOS, 2.56-2.66 pJ/bit, 13.6-16 Gb/s, BER < 10^-12

JSSC 2020第7期Wireline I/OEqualizer

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s Michiel V erplaetse , Student Member , IEEE,J o r i sL a m b r e c h t, Michael V anhoecke , Laurens Breyne , Student Member , IEEE

提出一种用于16-QAM光通信的55nm SiGe BiCMOS模拟I-Q FIR滤波器，补偿频率相关变化。

55nm BiCMOS, 185mW核心功耗, 112Gb/s 16-QAM调制信号

JSSC 2019第1期Wireline I/O

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)

2018年ISSCC会议精选论文集，涵盖高速有线收发器、光学技术和时钟生成等领域的进展。

64-Gb/s, 56-Gb/s, 112-Gb/s, 1.17-pJ/bit, 25-Gb/s/pin, 28-Gb/s

JSSC 2019第1期Wireline I/OSRAMDRAM

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

QUEST是一款采用3D堆叠技术的多用途对数量化DNN推理引擎，具有高带宽和低延迟特性。

7.49 TOPS（二进制精度）, 1.96 TOPS（4位精度）, 300MHz时钟频率

JSSC 2019第2期Wireline I/OEqualizerSRAM

A 7T-SRAM With Data-Write Technique by

提出一种通过电容耦合写入数据的7T-SRAM，解决电流冲突问题并提升稳定性。

24nm 3.3V CMOS, 1.5V/1.8V Vdd, 20ns/10ns cycle time, 18ns/10ns access time, 400 FIT/Mb SER

JSSC 2019第4期Wireline I/O

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity

提出一种基于频谱压缩多带复用的新型菊花链下行接口，实现高带宽、低功耗的NAND闪存存储系统。

12.8-Gb/s吞吐量，BER 10^-12，发射机功耗252.1mW，接收机总功耗375.7mW

JSSC 2019第7期Wireline I/O

A 1-pJ/bit 80-Gb/s 2 15 − 1 PRBS Generator With a Modiﬁed Cherry–Hooper

一款低功耗80Gb/s伪随机二进制序列生成器，采用改进Cherry-Hooper输出驱动，性能优异。

130nm SiGe, 1 pJ/bit, 80 Gb/s, 300-mV眼图开度, 0.6-ps rms抖动

JSSC 2019第11期Wireline I/OPAM-4Neural Network Accelerator

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ λ PAM-4

一款16nm FinFET CMOS工艺的线性TIA，支持100Gbs PAM-4光链路，具有高带宽、低噪声和低功耗特性。

16nm FinFET CMOS, 60.8mW功耗, 27GHz带宽, 16.7pA/√Hz输入噪声密度

JSSC 2018第4期Wireline I/OHigh-Speed Link

A 65 nm 10 Gbs 10 mm On Chip Serial Link Featuring a Digital Intensive

一篇关于65纳米工艺下10Gbps片上串行链路的JSSC论文

65nm CMOS, 10Gbps, 10mm

JSSC 2017第9期Wireline I/OPAM-4

A Reconfigurable 16 32 Gb s Dual Mode NRZ PAM4 SerDes in 65 nm CMOS

一篇关于在65纳米CMOS工艺中实现可重构16/32 Gb/s双模式NRZ/PAM4 SerDes的论文

16/32 Gb/s, 65nm CMOS

JSSC 2016第4期Wireline I/OHigh-Speed Link

A 38 mW Gbps Quad Channel 8513 Gbps Serial Link With a 5 Tap DFE and a 4

一篇关于38mW Gbps四通道8513 Gbps串行链路的IEEE JSSC论文，采用5抽头DFE和4抽头Tr技术。

38mW Gbps, 四通道8513 Gbps

JSSC 2016第4期Wireline I/O

A 4x9Gbps 1pJpb Hybrid NRZ Multi Tone IO With Crosstalk and ISI Reduction for D

一种4通道9Gbps、1pJ/bit的混合NRZ多音IO接口，具有降低串扰和ISI的特性

4x9Gbps, 1pJ/bit

JSSC 2015第1期Wireline I/ODRAM

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test

12V 8Gb 8通道128GB/s高带宽HBM堆叠DRAM，采用TSV阵列和微凸点接口技术。

8Gb, 8通道, 128GB/s, 1.2V

JSSC 2015第1期Wireline I/ODRAM

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation Tae-Y oung Oh, Hoeju Chung, Jun-Y oung Park, Ki-Won Lee, Seunghoon Oh, Su-Y eon Doo, Hyoung-Joo Kim, ChangY ong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-S oo Ha, Y oungRyeol Choi, Y oung-Chul Cho, Y ong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwangil Park, SeongJin Jang, and Joo

一款1.0V 8Gbit LPDDR4 SDRAM，支持3.2Gbps/pin速度并集成ECC引擎，适用于亚1V DRAM核心。

1.0V, 3.2Gbps/pin, 8Gbit

JSSC 2015第4期Wireline I/O

340 mV–1.1 V , 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4)2 Polynomials in 22 nm Tri-Gate CMOS

一款22纳米三栅极CMOS工艺的纳米AES硬件加速器，具有低功耗和高能效特性。

1.133 GHz最大操作频率，13 mW总功耗，289 Gbps/W能效

JSSC 2015第7期Wireline I/OEqualizer

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS Shayan Shahramian and Anthony

提出一种混合IIR和离散时间DFE的10Gb/s低功耗接收器设计。

28nm CMOS, 150mVpp-diff, 10Gb/s, 4.1mW, 24dB信道损耗

JSSC 2015第8期Wireline I/ODRAM

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Y oungbo Shim, Sangil Park, Bokr im Ko, Duckhwa Hong, Y ongsuk Joo, Wooyoung Lee, Y ongdeok Cho, Wooyeol Shin, Jaew oong Y un, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Namkyu Jang, Jaemo Y ang, Hae-k ang Jung, Joohwan Cho, Hyeongon Kim, and

本文提出了一种LPDDR4设计，通过多通道架构和低摆幅接口等技术，实现了39%的能效提升和4.3 Gbps的数据速率。

1.1 V, 4.3 Gbps

JSSC 2015第10期Wireline I/O

Comments and Corrections Correction to “A 0.41 pJ/Bi t 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS” Shayan Shahramian and Anthony Chan Carusone In the above paper [1], a mistake was made during printing and Fig. 9(b) was overwritten with Fig. 9(a). The correct Fig. 9 is shown below. In addition, Equation (4) should read: (4) IEEE regrets the errors.

对论文中图9和公式(4)的印刷错误进行更正。

JSSC 2014第2期Wireline I/OEqualizer

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer Ahmed Awny, Lothar Moeller, Joseph Junio, J.

设计并测量了用于80 Gb/s短距离光通信系统的1-tap决策反馈均衡器

80 Gb/s和110 Gb/s版本分别消耗4W和5.75W，面积分别为2 mm²和2.56 mm²

JSSC 2014第6期Wireline I/OEqualizer

A Low-Noise Design Technique for High-Speed CMOS

提出一种用于高速CMOS光接收器的低噪声设计技术，通过两阶段前端实现噪声与带宽的优化。

灵敏度-11.9 dBm @ BER, 跨阻增益83 dB, 25 Gb/s

JSSC 2014第12期Wireline I/OEqualizerNeural Network Accelerator

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

提出一种用于10 Gb/s的功率可扩展连续时间FIR均衡器，适用于多模光纤链路中的色散补偿。

28nm LP CMOS, 10-25 Gb/s, 55-90 mW

JSSC 2013第1期Wireline I/OPower Amplifier

The Next Generation 64b SPARC Core in a T4 SoC Processor Jinuk Luke Shin, Robert Golla, Hongping Li, Sudesna Dash, Y oungmoon Choi, Al an Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park , Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski , and Curtis McAllister

SPARC T4处理器采用新一代64位多线程核心，性能提升显著，集成多项高速I/O和电源管理技术。

3.0 GHz operation, 855 million transistors, 2.6 million flip-flops, 768 GB/sec crossbar, 2.4 Tb/s bandwidth

JSSC 2013第2期Wireline I/O

FEBRUARY 2013 VOLUME 48 NUMBER 2 IJSCBC ISSN 0018-9200 Ne w A s s o c i a te Edi

该期刊包含多篇关于高速低功耗通信电路设计的论文，涵盖接收器、信号处理等技术。

24Gb/s, 10Gb/s, 7.5Gb/s

JSSC 2013第3期Wireline I/O

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines Tsutomu Takeya, Student Member , IEEE,L a nN a n, Member , IEEE, Shinya Nakano

提出一种基于耦合传输线的高数据速率非接触接口，实现12 Gb/s通信速度

12 Gb/s, 1 mm通信距离, 3.4-9.0 GHz带宽

JSSC 2013第3期Wireline I/O

MARCH 2013 VOLUME 48 NUMBER 3 IJSCBC ISSN 0018-9200 Ne w A s s o c i a te Edi t

2013年IEEE JSSC期刊收录多篇前沿集成电路设计论文，涵盖高速接收器、唤醒接收器、ADC校准等技术。

['0.4mW/Gb/s', '16Gb/s', '247µW', '25Gb/s', '2.8-3.2GHz']

JSSC 2013第9期Wireline I/O

A 3.3/2.5 V-Supply 2400 mV-Swing Single-Ended SiGe BiCMOS Driver With Programmable Preemphasis for 3 Gb/s Data Transmission Over 75 Coaxial Cable Peter A. Davies , Senior Member , IEEE

一款3.3V供电、2400mV摆幅的单端SiGe BiCMOS电缆驱动器，支持可编程预加重。

3.3V供电, 2400mV摆幅, 270Mb/s-2.97Gb/s数据速率, 4kV HBM ESD防护

JSSC 2013第10期Wireline I/OFlash Memory

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Y oungjoo Lee, Student Member , IEEE, Hoyoung Y oo, Student Member , IEEE,J a ehwan Jung, Student Member , IEEE, Jihyuck Jo, Student Member , IEEE

65nm CMOS工艺下高效能迭代级联BCH解码器，用于NAND闪存纠错。

65nm CMOS, 17.7 Gb/s, 274 pJ/bit

JSSC 2013第12期Wireline I/OHigh-Speed Link

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced

28nm工艺下实现20Gb/s低功耗短距离单端串行链路，采用地参考信号技术。

28nm CMOS, 0.9V, 20Gb/s, 0.54pJ/bit, 4.5mm有机基板通道

JSSC 2013第12期Wireline I/O

A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS

32nm CMOS工艺下可扩展的64通道并行I/O芯片，实现1.024 Tb/s总带宽和2.6 pJ/bit能效

32nm CMOS, 1.08V/0.65V, 16 Gb/s每通道

JSSC 2013第12期Wireline I/OEqualizer

Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS Yu e L u, Student Member , IEEE

65nm CMOS工艺下实现66 Gb/s、46 mW功耗的3抽头判决反馈均衡器设计

66 Gb/s, 46 mW, 1.2V, 0.7 pJ/bit

JSSC 2012第1期Wireline I/ODRAM

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang Kyu Kang, So-Y oung Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo Sun Choi, and Y oung-Hyun Jun

一款1.2V 1Gb移动SDRAM，采用50nm技术，具有4通道512DQ引脚，实现12.8GB/s带宽。

1.2V, 12.8GB/s, 330.6mW

JSSC 2012第4期Wireline I/ODRAM

A 12.8-Gb/s/link Tri-Modal Single-Ended

一款支持三模式、12.8Gbps单端信号传输的内存接口控制器

12.8 Gbps, 5.0 mW/Gbps

JSSC 2012第4期Wireline I/O

A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder Chih-Lung Chen, Y u-Hsiang Lin, Hsie-Chia Chang

本文提出了一种高性能LDPC-CC解码器芯片，通过多级优化实现2.37Gb/s吞吐量。

90nm CMOS, 1.2V, 2.37Gb/s, 0.024nJ/bit

JSSC 2012第4期Wireline I/ODRAM

A Tri-Modal 20-Gbps/Link Differential/DDR3/ GDDR5

本文介绍了一种三模不对称双向差分内存接口，支持高达20 Gbps的数据传输速率。

40-nm CMOS, 20 Gbps, 6.1 mW/Gbps

JSSC 2012第6期Wireline I/O

A 5-Gb/s Automatic Gain Control Ampli ﬁer With Temperature Compensation Chang Liu, Y ue-Peng Y an

提出一种带温度补偿的5Gbps自动增益控制放大器，适用于高速应用。

40 dB增益, 7.5 GHz带宽, 72 mW功耗, 1.2V电源电压, 5Gb/s数据传输速率

JSSC 2012第9期Wireline I/ONeural Network Accelerator

A 5.79-Gb/s Energy-Efﬁcient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications Shao-Wei Yen, Shiang-Y u Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou

一款支持IEEE 802.15.3c四种码率的高效能LDPC编解码芯片，采用65nm工艺，最高吞吐量5.79Gb/s。

65nm CMOS, 5.79Gb/s吞吐量, 3.7Gb/s/mm²硬件效率, 62.4pJ/b能效

JSSC 2012第10期Wireline I/O

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card Andrzej Radecki, Student Member , IEEE,Y u x i a n g Y u a n, Member , IEEE

使用嵌套三叶草线圈实现6Gb/s数据和10mW功率同时传输的非接触式存储卡接口设计

6 Gb/s, 10 mW, 5.2%-10.2%效率

JSSC 2012第11期Wireline I/OProcessor/CPU

2.4 Gbps, 7 mW All-Digital PVT-V ariation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors Sanu K. Mathew , Member , IEEE

45nm CMOS工艺下全数字PVT变化容忍的真随机数生成器，实现2.4Gbps吞吐与2.9pJ/bit能效

45nm CMOS, 1.1V/280mV, 2.4Gbps@7mW(1.1V), 14Mbps@5.6µW(280mV)

JSSC 2012第12期Wireline I/O

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel

提出一种新型编码差分并行电信号传输方案，提升时序裕量并降低能耗。

40nm CMOS, 16 Gb/s, 4.1 pJ/b

JSSC 2011第1期Wireline I/O

A 40 nm 16-Core 128-Thread SPARC SoC Processor Jinuk Luke Shin

40纳米16核128线程SPARC SoC处理器，支持512线程系统，集成6MB L2缓存和高速I/O。

40nm工艺, 1.0V, 2.4Tb/s SerDes I/O

JSSC 2011第1期Wireline I/ODRAM

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction Tae-Y oung Oh, Y oung-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Y ong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Y oung-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Y oung Lee, Chang-Ho Shin, Y unseok Y ang, Beom-Sig Cho, Sam-Y oung Bang, Hyang-Ja Y ang, Y oung-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, and Y oung-Hyun Jun

介绍了一种1 Gbit GDDR5 SDRAM，支持7 Gb/s每引脚IO带宽，提升存储访问灵活性。

1.5 V电源供电，61.6 mm²/50die面积

JSSC 2011第2期Wireline I/O

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

本文通过非易失性FeRAM缓存提升硬盘性能，展示了128 Mb链式FeRAM设计及系统优化。

1.6 GB/s读/写带宽，512字节页长度，25%写能耗降低

JSSC 2011第4期Wireline I/OHigh-Speed LinkEqualizer

A 6.25 Gb/s V oltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links Sanquan Song, Student Member , IEEE, and Vladimir Stojanovic´, Member , IEEE

提出基于电压-时间转换的分数间隔线性接收均衡技术，用于高速链路中的联合均衡与相位同步。

90nm CMOS, 1.2V, 6.25Gb/s, 3.6mW/Gb/s, >4bit线性度

JSSC 2011第5期Wireline I/OProcessor/CPU

53 Gbps Native /71/70/40/50/52/41/50Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors Sanu K. Mathew , Member , IEEE

45nm CMOS工艺下的高性能AES加密解密硬件加速器，实现53 Gbps的AES-128性能

53/44/38 Gbps AES-128/192/256性能, 125 mW, 1.1 V, 50°C

JSSC 2011第5期Wireline I/O

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode

开发了一种5Gb/s源同步信号系统，采用新的时钟/数据偏差最小化技术，提高了高频传输抖动容忍度。

5Gb/s, TSMC 40nm LP CMOS

JSSC 2011第6期Wireline I/OEqualizer

Low-Power CMOS Equalizer Design for 20-Gb/s Systems

提出低功耗CMOS均衡器设计方法，用于20Gb/s系统。

20Gb/s, 40mW, 1V

JSSC 2011第10期Wireline I/ONeural Network Accelerator

A2 . 4 - V 60-Gb/s CMOS Driver With Digitally V ariable Amplitude and Pre-Emphasis Control at Multiple Peaking

一款支持数字可调幅度和预加重的60Gb/s CMOS驱动器设计与验证

60Gb/s, 54dB增益, 12.2mW/Gb/s能效, 10dB回波损耗

JSSC 2010第1期Wireline I/O

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes Hidehiro Shiga

展示了一种采用130nm工艺的16GB/s DDR2 128Mb链式FeRAM，具有可扩展的八位线和感应方案。

130nm 4-metal CMOS, 400MHz, 800Mb/s/pin

JSSC 2010第1期Wireline I/ODRAM

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques Rex Kho, David Boursin, Martin Brox

本文介绍了一种75nm工艺的7 Gb/s/pin 1 Gb GDDR5图形内存设备，通过多种电路设计优化技术提升带宽。

7 Gb/s/pin, 1 Gb GDDR5, 75nm DRAM

JSSC 2010第3期Wireline I/OEqualizerESD

An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS

65nm CMOS工艺下实现的7抽头40Gb/s前馈均衡器，功耗80mW。

65nm CMOS, 1V, 40Gb/s, 80mW

JSSC 2010第4期Wireline I/O

A 4.3 GB/s Mobile Memory Interface With Power-Efﬁcient

本文提出了一种4.3 GB/s的移动内存接口，通过快速低功耗状态转换实现高效带宽调节。

40nm低功耗CMOS技术, 3.3 mW/Gb/s能效, 4.3 GB/s带宽

JSSC 2010第7期Wireline I/O

A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition Joo-Young Kim, Student Member , IEEE , Junyoung Park , Student Member , IEEE , Seungjin Lee, Student Member , IEEE, Minsu Kim , Student Member , IEEE, Jinwook Oh , Student Member , IEEE

提出一种用于实时物体识别处理器的118.4 GB/s多播网络芯片(MC-NoC)，采用分层星环结合拓扑结构降低延迟和能耗。

118.4 GB/s带宽, 48mW功耗, 400MHz频率, 1.2V电压

JSSC 2010第10期Wireline I/O

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

一款65nm CMOS工艺的双模SFI5.2兼容SerDes芯片组，功耗3W，支持40Gb/s光收发器。

65nm CMOS, 3W, 21.5–22.3 Gb/s DQPSK, 39.8–44.6 Gb/s NRZ

JSSC 2010第12期Wireline I/O

New Associate Editors I T IS with pleasure that I welcome Dr Tony Chan Caru- son

IEEE JSSC期刊欢迎新任副编辑，介绍其专业背景与贡献。

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JSSC 2009第3期Wireline I/O

A High-Speed Inductive-Coupling Link With

一种高速电感耦合链路，在180nm CMOS工艺下实现11Gb/s的数据传输速率，通信距离达15米。

180nm CMOS, 11Gb/s, 15m

JSSC 2009第4期Wireline I/O

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric

一篇关于16 Gb/s双向非对称内存接口的IEEE JSSC论文，采用65nm CMOS工艺实现高性能数据传输。

16 Gb/s, 15 dB Nyquist损耗, 控制器13 mW/Gb/s, DRAM PHY 8 mW/Gb/s

JSSC 2009第6期Wireline I/O

Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder Sterling R. Whitaker , Senior Member , IEEE, Lowell H. Miles, Jody W. Gambles , Senior Member , IEEE, Paul Winterrowd, Ron Nelson, Chad Orbe, and Gary K. Maki , Senior Member , IEEE

一种抗辐射的16 Gbps低密度奇偶校验编码器设计

1.6 Gb/s, 线性能量转移阈值大于33 MeV cm²/mg

JSSC 2009第10期Wireline I/ONeural Network Accelerator

A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Ampliﬁer With Enlarged Input Capacitance Tolerance in 0.18 /22m CMOS Technology

本文提出了一种自补偿差分跨阻放大器设计，结合差分传感和自举技术，有效减少光电二极管和ESD保护电路的负载效应。

3.5 kΩ, 1.72 GHz, 3 Gb/s, 40 mW, 1.8 V

JSSC 2009第11期Wireline I/ODRAM

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel Y oung-Chan Jang, Hoeju Chung, Y oungdon Choi, Hwanwook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Y un Kim, Y un-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jeihwan Y oo

一篇关于5.8-Gbps/pin单向差分I/O在DRAM应用中的BER测量的研究论文。

5.8-Gb/s/pin操作

JSSC 2009第12期Wireline I/O

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

65nm CMOS工艺下实现支持40Gbs和双20Gbs输出的串行器芯片。

65nm CMOS, 1.2V/3.3V, 40Gbs(1.8W), 20Gbs(1.6W)

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