JSSC 分类

Wireline I/O

117 篇期刊论文

子分类 Subcategories
Equalizer
28 篇
High-Speed Link
7 篇
PAM-4
6 篇
Optical I/O
1 篇
JSSC 2025第3期Wireline I/O
A 112-Gb/s − 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
16nm FinFET CMOS工艺下112Gb/s 4-PAM线性TIA，支持下一代数据中心光接收器。
63-dBΩ增益, 32-GHz带宽, 16.9 pA/√Hz噪声密度, 0.9V供电, 47mW功耗
JSSC 2024第1期Wireline I/O
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%–99.99% Error Coverage in Intel 4 CMOS
一款抗故障注入攻击的AES-256加密引擎，采用Intel 4 CMOS工艺，实现100Gbps吞吐量和99.1%错误覆盖率。
Intel 4 CMOS, 100Gbps, 99.1% error coverage, 13,400× laser injection margin
JSSC 2024第5期Wireline I/OPAM-4
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS
28nm CMOS工艺下设计的非相干100Gbps双波段PAM-4塑料光纤链路
28nm CMOS, 100Gb/s@3m, 574mW, BER<2.2e-4
JSSC 2024第7期Wireline I/O
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method
一款基于StrongARM锁存比较器和平方取中法的10Gb/s全数字真随机数生成器
28nm CMOS, 10Gb/s吞吐量, 0.121pJ/bit能效
JSSC 2024第10期Wireline I/ODRAM
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications Hyun-A Ahn
提出第四代10nm 16Gb LPDDR5x DRAM的I/O电路和控制方法，实现8.5Gbps低功耗运行。
8.5Gbps, 0.66UI Tx眼宽, 0.57UI Rx眼宽, 功耗降低20%
JSSC 2023第1期Wireline I/OFlash Memory
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface Jong Hak Y uh , Y en-Lung Jason Li, Heguang Li, Y oshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Y eong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Y ap, Demin Wang, Steve Kim, Y onggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu , Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen , Indra K. V ., V . S. N. K. Chaitanya G., V enky Ramachandra, Y osuke Kato, Ravi J. Kumar, Huijuan Wang, Farookh Moogat, In-Soo Y oon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Y anagidaira, Takuyo Kodama
1Tb 4位/单元162层3D闪存，采用中央阶梯结构和CTW架构，实现15Gb/mm²面密度和60MB/s编程吞吐量。
15Gb/mm²面密度，60MB/s编程吞吐量，65µs最佳tR，2.4Gb/s IO速度
JSSC 2023第1期Wireline I/ODRAM
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based
介绍了一种192-Gb 896-GB/s的HBM3 DRAM，采用低功耗高可靠性设计。
192-Gb 896-GB/s 1.0-V
JSSC 2023第4期Wireline I/ODRAM
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features Yesin Ryu , Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim , Hyochang Kim , Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong , Sunghwan Joo , Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim , Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn , Sang-Joon Hwang
本文提出了一种16GB HBM3 DRAM设计，通过源同步总线和片上纠错技术实现1024 GB/s带宽。
16GB容量，1024 GB/s带宽，8 Gb/s/pin，105°C高温稳定运行
JSSC 2023第4期Wireline I/O
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS
Intel 4 CMOS工艺下7Gbps抗侧信道攻击的乘法掩码AES引擎
7Gbps, 65%面积开销, 4%性能开销
JSSC 2023第9期Wireline I/OOptical I/O
New Associate Editor I
Samuel Palermo教授成为IEEE JSSC期刊的新任副主编，专注于高速SerDes电路和硅光子互连技术。
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JSSC 2023第11期Wireline I/O
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s Ji-Young Kim
提出一种低功耗TSV I/O设计，用于HBM，数据速率达10Gb/s。
65nm CMOS, 0.179–0.185 pJ/b/pF, 5–10 Gb/s
JSSC 2022第1期Wireline I/OEqualizerPAM-4
A 112-Gbs PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline R
本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。
112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b
JSSC 2022第1期Wireline I/OPAM-4DRAM
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido
通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。
22 Gbps per-pin data rate
JSSC 2022第2期Wireline I/O
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
开发适用于工业机器人手臂的6 Gb/s旋转非接触连接器，实现高速可靠无线数据传输。
40 nm CMOS, BER < 10^-12, 3 mm通信距离
JSSC 2022第5期Wireline I/OPAM-4Neural Network Accelerator
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS
22nm FinFET CMOS工艺下实现的高能效128Gb/s单端PAM4线性TIA
22nm FinFET CMOS, 0.8V, 128Gb/s PAM4, 59.3dBΩ增益, 11.2mW功耗, 45.5GHz带宽, 27μArms输入噪声
JSSC 2022第6期Wireline I/OEmerging MemoryNeural Network Accelerator
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device Y en-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang
22纳米1Mb 1024位读取数据保护的STT-MRAM宏，采用近存移位旋转功能降低峰值电流和能耗。
42.67 GB/s读取带宽，0.23 pJ/bit能效
JSSC 2022第6期Wireline I/O
A 5 Gb/s Time-Interleaved V oltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC Ji-Y
提出一种用于3D堆叠内存的低功耗双二进制编码方案，实现5Gb/s高速传输。
65nm CMOS, 5Gb/s, 0.373pJ/b/pF
JSSC 2021第1期Wireline I/ODRAM
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme Ki Chul Chun , Y ong Ki Kim, Y esin Ryu, Jaewon Park, Chi Sung Oh, Y oung Y ong Byun, So Y oung Kim, Dong Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Soo Y oung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun
介绍了一种16GB 640GB/s的HBM2E DRAM，采用数据总线窗口扩展技术和同步设计，提升性能和可靠性。
16GB容量，640GB/s带宽，5Gb/s/引脚，105°C高温稳定运行
JSSC 2021第3期Wireline I/O
A Simultaneous Bidirec tional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s
130nm BiCMOS工艺实现24Gb/s双向同轴链路，支持直流供电。
24Gb/s, 0.7 UIpp抖动容限, 18.3dB损耗, BER<10–12, 141.25mW功耗
JSSC 2021第4期Wireline I/OFlash Memory
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage Daehoon Na , Jang-woo Lee, Seon-Kyoo Lee, Hwasuk Cho, Junha Lee, Manjae Y ang, Eunjin Song, Anil Kavala, Tongsung Kim, Dong-Su Jang, Y oungmin Jo, Ji-Y eon Shin, Byung-Kwan Chun, Tae-sung Lee, Byunghoon Jeong, Chi-Weon Y oon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae Seok Byeon, Jinyub Lee, and Jai
本文提出了一种1.2V、1.8Gb/s/pin的16Tb NAND闪存多芯片封装方案，采用第三代F-chip提升性能。
1.2V, 1.8Gb/s/pin, 16Tb
JSSC 2021第8期Wireline I/OEqualizerDRAM
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer Hyeongjun Ko , Mino Kim
提出一种用于高容量DRAM的控制器PHY，采用阻尼电阻辅助脉冲前馈均衡器减少信号干扰。
1067 Mb/s时C/A信号时序裕量从0.23 UI提升至0.29 UI，2133 Mb/s时DQ信号读写时序裕量分别为0.53 UI和0.72 UI
JSSC 2020第1期Wireline I/ODRAM
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With V arious High-Speed and Low-Power Techniques Kyung-Soo Ha , Chang-Kyo Lee , Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Y oung-Hwa Kim, Y oung Hoon Son, Byongwook Na, Seungseob Lee, Y oun-Sik Park, Hyuck-Joon Kwon, Tae-Y oung Oh, Y oung-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, and Jung-Bae Lee
本文介绍了一种采用1xnm DRAM工艺的8Gb LPDDR5 SDRAM，通过多种高速和低功耗技术实现7.5 Gb/s/pin的带宽。
7.5 Gb/s/pin, 8-Gb, 21% read power reduction, 33% write power reduction, 25% self-refresh power reduction
JSSC 2020第3期Wireline I/OEqualizer
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication—Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit Yusang Chun , Student Member , IEEE
提出一种无需均衡器的ISI弹性Dicode编码方案，用于低带宽有线通信。
65-nm CMOS, 2.56-2.66 pJ/bit, 13.6-16 Gb/s, BER < 10^-12
JSSC 2020第7期Wireline I/OEqualizer
Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s Michiel V erplaetse , Student Member , IEEE,J o r i sL a m b r e c h t, Michael V anhoecke , Laurens Breyne , Student Member , IEEE
提出一种用于16-QAM光通信的55nm SiGe BiCMOS模拟I-Q FIR滤波器，补偿频率相关变化。
55nm BiCMOS, 185mW核心功耗, 112Gb/s 16-QAM调制信号
JSSC 2019第1期Wireline I/OPLLEqualizer
A 16-Gb 18-Gbps per pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and P
16Gb GDDR6 DRAM采用每比特可训练单端DFE和ZQ编码发射器，实现18Gbps/pin高速操作
16 Gb/s/pin @1.15V, 18 Gb/s/pin @1.35V
JSSC 2019第4期Wireline I/O
A 128-Gbps Daisy Chain-Based Downlink IF Employing Spectrally Compressed Multi-B
提出一种基于频谱压缩多带复用的新型菊花链下行接口，实现高带宽、低功耗的NAND闪存存储系统。
12.8-Gb/s吞吐量，BER 10^-12，发射机功耗252.1mW，接收机总功耗375.7mW
JSSC 2019第7期Wireline I/O
A 1-pJ/bit 80-Gb/s 2 15 − 1 PRBS Generator With a Modified Cherry–Hooper
一款低功耗80Gb/s伪随机二进制序列生成器，采用改进Cherry-Hooper输出驱动，性能优异。
130nm SiGe, 1 pJ/bit, 80 Gb/s, 300-mV眼图开度, 0.6-ps rms抖动
JSSC 2019第9期Wireline I/O
Analysis and Design of Wideband I/Q CMOS 100–200 Gb/s Modulators Hasan Al-Rubaye and Gabriel M. Rebeiz
本文介绍了一种宽带I/Q CMOS调制器的分析与设计，适用于下一代无线回程链路。
60 dB动态范围，1-GHz带宽，OP1dB ∼−10 dBm，200 Gb/s 16-QAM
JSSC 2019第11期Wireline I/OPAM-4Neural Network Accelerator
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ λ PAM-4
一款16nm FinFET CMOS工艺的线性TIA，支持100Gbs PAM-4光链路，具有高带宽、低噪声和低功耗特性。
16nm FinFET CMOS, 60.8mW功耗, 27GHz带宽, 16.7pA/√Hz输入噪声密度
JSSC 2018第4期Wireline I/OHigh-Speed Link
A 65 nm 10 Gbs 10 mm On Chip Serial Link Featuring a
一篇关于65纳米工艺下10Gbps片上串行链路的JSSC论文
65nm CMOS, 10Gbps, 10mm
JSSC 2017第2期Wireline I/O
460 A 40 Gb s SiGe BiCMOS MZM Driver With 6 Vpp Output and
一款460A、40Gb/s SiGe BiCMOS MZM驱动器，输出6Vpp并集成片上数字校准功能。
460A, 40Gb/s, 6Vpp
JSSC 2017第4期Wireline I/OHigh-Speed Link
A 16 Gbs 147 mW Tri Band Cognitive Serial Link
一款16 Gbps、147 mW的三频段认知串行链路发射器，采用转发时钟技术
16 Gbps, 147 mW
JSSC 2017第5期Wireline I/O
A 28 mW Gb s 14 Gb s Serial
一款28mW功耗、支持1-14Gb/s速率的串行链路收发器
28mW, 1-14Gb/s
JSSC 2017第9期Wireline I/O
A 40 Gb s 14 mW CMOS
一款40Gb/s、14mW的CMOS有线接收器
40Gb/s, 14mW
JSSC 2017第9期Wireline I/OPAM-4
A Reconfigurable 16 32 Gb s Dual Mode NRZ PAM4 SerDes in 65 nm CMOS
一篇关于在65纳米CMOS工艺中实现可重构16/32 Gb/s双模式NRZ/PAM4 SerDes的论文
16/32 Gb/s, 65nm CMOS
JSSC 2017第9期Wireline I/O
W Band Direct Modulation 20 Gb s Transmit and Receive Building Blocks in 32 nm
32纳米工艺下实现W波段20Gb/s直接调制收发器模块
32nm CMOS, 20Gb/s
JSSC 2017第12期Wireline I/O
Design Techniques for a 60 Gbs 288 mW NRZ
设计一个60 Gbps、288 mW NRZ收发器，采用自适应均衡技术
60 Gbps, 288 mW
JSSC 2016第1期Wireline I/OFlash Memory
A 128 Gb 3b cell V NAND Flash Memory With 1 Gb s IO Rate
该论文介绍了一种128Gb 3b单元V-NAND闪存，支持1Gb/s的IO速率。
128Gb, 3b cell, 1Gb/s IO rate
JSSC 2016第4期Wireline I/OHigh-Speed Link
A 38 mW Gbps Quad Channel 8513 Gbps Serial Link With a 5 Tap DFE and a 4
一篇关于38mW Gbps四通道8513 Gbps串行链路的IEEE JSSC论文，采用5抽头DFE和4抽头Tr技术。
38mW Gbps, 四通道8513 Gbps
JSSC 2016第4期Wireline I/O
A 4x9Gbps 1pJpb Hybrid NRZ Multi Tone IO With Crosstalk and ISI Reduction for D
一种4通道9Gbps、1pJ/bit的混合NRZ多音IO接口，具有降低串扰和ISI的特性
4x9Gbps, 1pJ/bit
JSSC 2016第9期Wireline I/O
55 nm SiGe BiCMOS Distributed Amplifier Topologies for Time Interleaved 120 Gbs
55 nm SiGe BiCMOS分布式放大器拓扑结构用于时间交织120 Gbps应用
120 Gbps
JSSC 2016第11期Wireline I/O
A 03 pJbit 20 GbsWire Parallel Interface for Die to
提出一种用于芯片间通信的20 Gbps低功耗并行接口
0.3 pJ/bit, 20 Gbps
JSSC 2015第1期Wireline I/ODRAM
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test
12V 8Gb 8通道128GB/s高带宽HBM堆叠DRAM，采用TSV阵列和微凸点接口技术。
8Gb, 8通道, 128GB/s, 1.2V
JSSC 2015第1期Wireline I/ODRAM
A 32 Gbpspin 8 Gbit 10 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRA
一款1.0V 8Gbit LPDDR4 SDRAM，支持3.2Gbps/pin速度并集成ECC引擎，适用于亚1V DRAM核心。
1.0V, 3.2Gbps/pin, 8Gbit
JSSC 2015第2期Wireline I/OEqualizer
A 25 Gbs 58 mW CMOS Equalizer
一款采用45nm工艺的低功耗25Gbps CMOS均衡器设计
25Gbps, 58mW, 1V供电, 24dB损耗补偿
JSSC 2015第4期Wireline I/O
340 mV11 V 289 GbpsW 2090-Gate NanoAES Hardware Accelerator With Area-Optimized
一款22纳米三栅极CMOS工艺的纳米AES硬件加速器，具有低功耗和高能效特性。
1.133 GHz最大操作频率，13 mW总功耗，289 Gbps/W能效
JSSC 2015第7期Wireline I/OEqualizer
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS Shayan Shahramian and Anthony
提出一种混合IIR和离散时间DFE的10Gb/s低功耗接收器设计。
28nm CMOS, 150mVpp-diff, 10Gb/s, 4.1mW, 24dB信道损耗
JSSC 2015第8期Wireline I/ODRAM
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Y oungbo Shim, Sangil Park, Bokr im Ko, Duckhwa Hong, Y ongsuk Joo, Wooyoung Lee, Y ongdeok Cho, Wooyeol Shin, Jaew oong Y un, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Namkyu Jang, Jaemo Y ang, Hae-k ang Jung, Joohwan Cho
本文提出了一种LPDDR4设计，通过多通道架构和低摆幅接口等技术，实现了39%的能效提升和4.3 Gbps的数据速率。
1.1 V, 4.3 Gbps
JSSC 2015第10期Wireline I/O
Comments and Corrections Correction to “A 0.41 pJ/Bi t 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS” Shayan Shahramian and Anthony Chan Carusone In the above paper [1], a mistake was made during printing and Fig. 9(b) was overwritten with Fig. 9(a). The correct Fig. 9 is shown below. In addition, Equation (4) should read: (4) IEEE regrets the errors.
对论文中图9和公式(4)的印刷错误进行更正。
JSSC 2014第1期Wireline I/O
A 36 GHz 16-Core SPARC SoC Processor in 28 nm
Oracle推出28nm工艺的16核SPARC T5处理器，性能提升显著。
28nm CMOS, 3.6GHz, 1.5 billion transistors, 5.65 TB/sec bandwidth
JSSC 2014第2期Wireline I/OEqualizer
Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer Ahmed Awny, Lothar Moeller, Joseph Junio, J.
设计并测量了用于80 Gb/s短距离光通信系统的1-tap决策反馈均衡器
80 Gb/s和110 Gb/s版本分别消耗4W和5.75W，面积分别为2 mm²和2.56 mm²
JSSC 2014第12期Wireline I/OHigh-Speed Link
A 1522 Gbps Serial Link in 28 nm CMOS With Direct DFE
28nm CMOS工艺下实现1522 Gbps半双工串行链路设计，支持20 dB损耗PCB信道。
28nm CMOS, 1.35V/0.9V, 20 Gbps, 6.5 mW/Gbps
JSSC 2014第12期Wireline I/OEqualizer
A 28 Gbs 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-
28nm CMOS工艺下实现28 Gb/s多标准SerDes，功耗560 mW/通道。
28 Gbps, 560 mW/lane, 34 dB channel loss
JSSC 2014第12期Wireline I/OEqualizerNeural Network Accelerator
Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS
提出一种用于10 Gb/s的功率可扩展连续时间FIR均衡器，适用于多模光纤链路中的色散补偿。
28nm LP CMOS, 10-25 Gb/s, 55-90 mW
JSSC 2013第3期Wireline I/O
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines Tsutomu Takeya, Student Member , IEEE,L a nN a n, Member , IEEE, Shinya Nakano
提出一种基于耦合传输线的高数据速率非接触接口，实现12 Gb/s通信速度
12 Gb/s, 1 mm通信距离, 3.4-9.0 GHz带宽
JSSC 2013第9期Wireline I/O
A 3.3/2.5 V-Supply 2400 mV-Swing Single-Ended SiGe BiCMOS Driver With Programmable Preemphasis for 3 Gb/s Data Transmission Over 75 Coaxial Cable Peter A. Davies , Senior Member , IEEE
一款3.3V供电、2400mV摆幅的单端SiGe BiCMOS电缆驱动器，支持可编程预加重。
3.3V供电, 2400mV摆幅, 270Mb/s-2.97Gb/s数据速率, 4kV HBM ESD防护
JSSC 2013第10期Wireline I/OFlash Memory
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Y oungjoo Lee, Student Member , IEEE, Hoyoung Y oo, Student Member , IEEE,J a ehwan Jung, Student Member , IEEE, Jihyuck Jo, Student Member , IEEE
65nm CMOS工艺下高效能迭代级联BCH解码器，用于NAND闪存纠错。
65nm CMOS, 17.7 Gb/s, 274 pJ/bit
JSSC 2013第12期Wireline I/OHigh-Speed Link
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced
28nm工艺下实现20Gb/s低功耗短距离单端串行链路，采用地参考信号技术。
28nm CMOS, 0.9V, 20Gb/s, 0.54pJ/bit, 4.5mm有机基板通道
JSSC 2013第12期Wireline I/OEqualizer
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS Yu e L u, Student Member , IEEE
65nm CMOS工艺下实现66 Gb/s、46 mW功耗的3抽头判决反馈均衡器设计
66 Gb/s, 46 mW, 1.2V, 0.7 pJ/bit
JSSC 2012第1期Wireline I/ODRAM
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang Kyu Kang, So-Y oung Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo Sun Choi, and Y oung-Hyun Jun
一款1.2V 1Gb移动SDRAM，采用50nm技术，具有4通道512DQ引脚，实现12.8GB/s带宽。
1.2V, 12.8GB/s, 330.6mW
JSSC 2012第4期Wireline I/OClock GenerationEqualizer
A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS Chintan Thakkar, Student Member , IEEE ,L i n g k a i K o n g, Student Member , IEEE , Kwangmo Jung, Student Member , IEEE, Antoine Frappé , Member , IEEE
65纳米CMOS工艺下实现10Gbps低功耗60GHz基带设计
10 Gb/s, 45 mW (adaptation off), 53 mW (adaptation on)
JSSC 2012第4期Wireline I/O
A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder Chih-Lung Chen, Y u-Hsiang Lin, Hsie-Chia Chang
本文提出了一种高性能LDPC-CC解码器芯片，通过多级优化实现2.37Gb/s吞吐量。
90nm CMOS, 1.2V, 2.37Gb/s, 0.024nJ/bit
JSSC 2012第4期Wireline I/O
A 26 mWGbps 125 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS Thomas T
32nm SOI CMOS工艺下的低功耗接收器电路，采用8抽头开关电容DFE，支持12.5 Gbps数据传输。
32nm CMOS, 1.1V, 12.5 Gb/s, 2.6 mW/Gbps
JSSC 2012第4期Wireline I/ODRAM
A Tri-Modal 20-GbpsLink DifferentialDDR3 GDDR5 Memory Interface Kambiz Kaviani M
本文介绍了一种三模不对称双向差分内存接口，支持高达20 Gbps的数据传输速率。
40-nm CMOS, 20 Gbps, 6.1 mW/Gbps
JSSC 2012第4期Wireline I/O
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects Timothy O. Dickson , Member , IEEE,Y o n g L i u, Member , IEEE, Sergey V . Rylov , Member , IEEE
基于高密度硅载体的8x10-Gbs源同步IO系统，采用先进硅封装技术实现高密度互连。
8x10-Gb/s, 5.3 pJ/bit, 1 V TX/RX电源
JSSC 2012第6期Wireline I/O
A 5-Gb/s Automatic Gain Control Ampli fier With Temperature Compensation Chang Liu, Y ue-Peng Y an
提出一种带温度补偿的5Gbps自动增益控制放大器，适用于高速应用。
40 dB增益, 7.5 GHz带宽, 72 mW功耗, 1.2V电源电压, 5Gb/s数据传输速率
JSSC 2012第9期Wireline I/ONeural Network Accelerator
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications Shao-Wei Yen, Shiang-Y u Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou
一款支持IEEE 802.15.3c四种码率的高效能LDPC编解码芯片，采用65nm工艺，最高吞吐量5.79Gb/s。
65nm CMOS, 5.79Gb/s吞吐量, 3.7Gb/s/mm²硬件效率, 62.4pJ/b能效
JSSC 2012第10期Wireline I/O
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card Andrzej Radecki, Student Member , IEEE,Y u x i a n g Y u a n, Member , IEEE
使用嵌套三叶草线圈实现6Gb/s数据和10mW功率同时传输的非接触式存储卡接口设计
6 Gb/s, 10 mW, 5.2%-10.2%效率
JSSC 2012第11期Wireline I/O
24 Gbps 7 mW All-Digital PVT-V ariation Tolerant True Random Number Generator fo
45nm CMOS工艺下全数字PVT变化容忍的真随机数生成器，实现2.4Gbps吞吐与2.9pJ/bit能效
45nm CMOS, 1.1V/280mV, 2.4Gbps@7mW(1.1V), 14Mbps@5.6µW(280mV)
JSSC 2011第1期Wireline I/ODRAM
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction Tae-Y oung Oh, Y oung-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Y ong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Y oung-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Y oung Lee, Chang-Ho Shin, Y unseok Y ang, Beom-Sig Cho, Sam-Y oung Bang, Hyang-Ja Y ang, Y oung-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, and Y oung-Hyun Jun
介绍了一种1 Gbit GDDR5 SDRAM，支持7 Gb/s每引脚IO带宽，提升存储访问灵活性。
1.5 V电源供电，61.6 mm²/50die面积
JSSC 2011第4期Wireline I/O
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18- m CMOS Technology Shih-Hao Huang, Wei-Zen Chen, Y u-Wei Chang, and Y ang-Tung Huang
一款采用0.18微米CMOS工艺的10Gb/s全集成光接收机，包含新型网状空间调制光电探测器和高增益跨阻放大器。
6.9GHz带宽/29mA/W响应度/-6dBm灵敏度@10-12 BER
JSSC 2011第4期Wireline I/OHigh-Speed LinkEqualizer
A 6.25 Gb/s V oltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links Sanquan Song, Student Member , IEEE, and Vladimir Stojanovic´, Member , IEEE
提出基于电压-时间转换的分数间隔线性接收均衡技术，用于高速链路中的联合均衡与相位同步。
90nm CMOS, 1.2V, 6.25Gb/s, 3.6mW/Gb/s, >4bit线性度
JSSC 2011第5期Wireline I/O
53 Gbps Native 71704050524150Composite-Field AES-EncryptDecrypt Accelerator for
45nm CMOS工艺下的高性能AES加密解密硬件加速器，实现53 Gbps的AES-128性能
53/44/38 Gbps AES-128/192/256性能, 125 mW, 1.1 V, 50°C
JSSC 2011第5期Wireline I/O
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode
开发了一种5Gb/s源同步信号系统，采用新的时钟/数据偏差最小化技术，提高了高频传输抖动容忍度。
5Gb/s, TSMC 40nm LP CMOS
JSSC 2011第6期Wireline I/OEqualizer
Low-Power CMOS Equalizer Design for 20-Gbs Systems
提出低功耗CMOS均衡器设计方法，用于20Gb/s系统。
20Gb/s, 40mW, 1V
JSSC 2011第8期Wireline I/OEqualizer
Fully Digital Transmit Equalizer With Dynamic Impedance Modulation Ranko Sredojević, Student Member , IEEE, and Vladimir Stojanovi ć,M e m b e r ,IEEE
该论文提出了一种全数字传输均衡器，采用动态阻抗调制技术，实现了高能效的信号传输。
4 Gb/s, 2 pJ/bit, 100 mV接收眼图
JSSC 2011第10期Wireline I/ONeural Network Accelerator
A2 . 4 - V 60-Gb/s CMOS Driver With Digitally V ariable Amplitude and Pre-Emphasis Control at Multiple Peaking
一款支持数字可调幅度和预加重的60Gb/s CMOS驱动器设计与验证
60Gb/s, 54dB增益, 12.2mW/Gb/s能效, 10dB回波损耗
JSSC 2011第11期Wireline I/OEqualizer
A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band Ji-Hoon Park,S t u d e n tM e m b e r ,I E E E
设计了一种用于60 GHz频段的数字LOS/NLOS均衡器，支持2 Gb/s数据传输，功耗56 mW。
65nm CMOS, 2 Gb/s, 5.6 mW
JSSC 2011第12期Wireline I/O
A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Hiroyuki Yamagishi, Satoru Shinke
展示了一种基于塑料波导的新型互连解决方案，实现全双工12.5 Gb/s数据传输。
40nm CMOS, 57/80 GHz载频, 0.41mm²面积, 140mW功耗, 12.5Gb/s全双工
JSSC 2010第1期Wireline I/O
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes Hidehiro Shiga
展示了一种采用130nm工艺的16GB/s DDR2 128Mb链式FeRAM，具有可扩展的八位线和感应方案。
130nm 4-metal CMOS, 400MHz, 800Mb/s/pin
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