子分类 · Wireline I/O

High-Speed Link

47 篇相关 JSSC 论文

JSSC 2025第3期RF & WirelessHigh-Speed Link
A Jitter-Robust 40 Gbs ADC-Based Multicarrier Receiver Front-End With 4-GSs Base
一种抗抖动40Gbps多载波接收前端，采用4GS/s基带和优化ADC设计。
22nm FinFET, 40Gb/s, 1.6-ps rms抖动容限, BER<10-5, 3.05-pJ/bit能效
JSSC 2024第1期RF & WirelessHigh-Speed LinkEqualizer
A 112-Gbs Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for
一款支持112 Gb/s的多标准串行链路收发器，采用7nm FinFET工艺，功耗和面积效率高。
112 Gb/s, 43.9-dB IL补偿, 690-mW功耗, 0.63-mm²面积
JSSC 2024第5期RF & WirelessHigh-Speed Link
Parallel Versus Serial Design of an Optical Receiver With Integrated Blue Photod
比较并行与串行光链路的能效，提出集成蓝光光电探测器的并行光接收机设计。
130nm CMOS SOI, 2Gbps, -19.3dBm灵敏度, 0.5pJ/bit能效
JSSC 2024第8期RF & WirelessHigh-Speed LinkPAM-4
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Different
一种采用共模NRZ和差分PAM-4混合信号实现3比特/符号传输的线缆收发器。
28nm CMOS, 48 Gb/s, 0.117 mm², BER 10⁻¹² at 9.0
JSSC 2024第8期RF & WirelessHigh-Speed Link
An SNR-Enhanced 8-Ary SNRE-8 Modulation Technique for Wireline Transceivers Usin
提出一种新型八进制调制技术SNRE-8，通过调制脉冲宽度、位置和幅度提升信噪比。
27-Gb/s, BER 10^-8, 5.39 pJ/bit
JSSC 2023第1期RF & WirelessHigh-Speed LinkEqualizer
A 229-pJb 112-Gbs Wireline Transceiver With RX Four-Tap FFE for Medium-Reach App
一款用于中短距离电气链路的112Gb/s PAM-4收发器，采用RX四抽头FFE和两阶段16路交织技术。
28nm CMOS, 112Gb/s, BER<1e-11, 20.8dB信道损耗, 2.29pJ/b能效
JSSC 2023第3期RF & WirelessHigh-Speed Link
A Jitter-Robust 40 Gb-s ADC-Based Multicarrier Receiver Front-End With 4-GS-s Ba
一种抗抖动40Gb/s基于ADC的多载波接收前端，支持三频带信号传输。
22nm FinFET, 40Gb/s, 4GS/s, BER<10-5, 3.05pJ/bit
JSSC 2023第8期RF & WirelessHigh-Speed Link
A 090-Tbsin 129-pJb Wireline Transceiver With Single-Ended Crosstalk Cancellatio
提出一种采用斐波那契编码的单端串扰消除技术的高密度互连收发器。
28nm CMOS, 0.90 Tb/s/in, 1.29 pJ/b, BER<10−12
JSSC 2022第5期RF & WirelessHigh-Speed LinkEqualizer
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Dom
提出一种采用PWM技术的PAM-8有线收发器，通过时间域前馈均衡提高线性度。
12.0至39.6 Gb/s，补偿14-dB损耗，6.6 GHz，8.66 pJ/bit效率
JSSC 2021第1期RF & WirelessHigh-Speed LinkPAM-4
A 112-Gbs PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved
7nm FinFET CMOS工艺下实现的112Gb/s PAM-4长距离有线收发器
112Gb/s PAM-4, <1E-8 PRBS-31 BER, 37.5dB损耗@28GHz, 602mW/通道
JSSC 2020第7期RF & WirelessHigh-Speed LinkEqualizer
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for C
提出一种基于时钟域编码的iPWM线编码方案，实现低电压下的高效均衡。
3–16 Gb/s, 0.5-0.9V, 27dB channel loss, 1.8 pJ/bit
JSSC 2019第1期Wireline I/OHigh-Speed Link
A 117-pJ per b 25-Gbps per pin Ground-Referenced Single-Ended Serial Link for Of
16nm FinFET CMOS技术下的25 Gb/s/pin低能耗短距离串行链路
16nm FinFET CMOS, 25 Gb/s/pin, 1.17 pJ/bit
JSSC 2019第1期RF & WirelessSAR ADCHigh-Speed Link
A Fully Adaptive 1958-Gbps PAM-4 and 9529-Gbps NRZ Wireline Transceiver With Con
一款16nm FinFET工艺的双模PAM-4/NRZ收发器，支持19-58Gb/s PAM-4和9.5-29Gb/s NRZ传输。
16nm FinFET, <1e-12 BER, 9.7 pJ/bit
JSSC 2018第4期Wireline I/OHigh-Speed Link
A 65 nm 10 Gbs 10 mm On Chip Serial Link Featuring a Digital Intensive Time Bas
一篇关于65纳米工艺下10Gbps片上串行链路的JSSC论文
65nm CMOS, 10Gbps, 10mm
JSSC 2017第4期RF & WirelessHigh-Speed Link
A 16 Gbs 147 mW Tri Band Cognitive Serial Link Transmitter With Forwarded Clock
一款16 Gbps、147 mW的三频段认知串行链路发射器，采用转发时钟技术
16 Gbps, 147 mW
JSSC 2017第4期RF & WirelessSAR ADCHigh-Speed Link
A 56 Gbs PAM4 Wireline Transceiver Using a 32 Way Time Interleaved SAR ADC in 1
本文介绍了一种采用32路时间交织SAR ADC的56 Gbps PAM4有线收发器。
56 Gbps, 32-way time-interleaved SAR ADC
JSSC 2017第5期RF & WirelessHigh-Speed Link
A 28 mW Gb s 14 Gb s Serial Link Transceiver
一款28mW功耗、支持1-14Gb/s速率的串行链路收发器
28mW, 1-14Gb/s
JSSC 2016第4期Wireline I/OHigh-Speed Link
A 38 mW Gbps Quad Channel 8513 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Tr
一篇关于38mW Gbps四通道8513 Gbps串行链路的IEEE JSSC论文，采用5抽头DFE和4抽头Tr技术。
38mW Gbps, 四通道8513 Gbps
JSSC 2016第10期Clocking & PLLsHigh-Speed Link
A 76 mW 414 fs RMS Jitter 10 GHz Phase Locked Loop for a 40 Gb s Serial Link Tr
一款用于40Gb/s串行链路的低功耗、低抖动10GHz锁相环设计
76mW功耗, 414fs RMS抖动, 10GHz频率
JSSC 2015第2期RF & WirelessHigh-Speed LinkEqualizer
425 Gbs Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Tech
本文介绍了一种用于100 GbE系统的4×25 Gb/s全集成收发器芯片组，采用65 nm CMOS工艺。
65 nm CMOS, 4×25 Gb/s, 100 GbE标准
JSSC 2015第2期RF & WirelessHigh-Speed Link
A 6 Gbs Transceiver With a Nonlinear Electronic Dispersion Compensator for Direc
设计了一种6 Gb/s收发器，采用非线性电子色散补偿器，用于直接调制分布式反馈激光器。
6 Gb/s, 68 mW, 1 V supply, 14.69 dB optical SNR gain
JSSC 2015第4期RF & WirelessHigh-Speed LinkEqualizer
A 40 Gbs Serial Link Transceiver in 28 nm CMOS Technology Reza Navid Senior Mem
本文介绍了一种40 Gb/s的串行链路收发器，采用28 nm CMOS工艺，优化了芯片间通信并补偿20 dB信道损耗。
28nm CMOS, 40 Gb/s, 23.2 mW/Gb/s, 0.27 UI水平眼图开口, 120 mV垂直眼图开口
JSSC 2015第4期RF & WirelessHigh-Speed Link
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10
通过片上测量技术实现亚皮秒级时钟和数据抖动的精确测量。
RMS随机抖动0.85ps至1.89ps，正弦抖动0.89ps至5.1ps，误差小于0.6ps
JSSC 2015第12期RF & WirelessHigh-Speed LinkEqualizer
A 28 Gbs Multistandard Serial Link Transceiver for Backplane Applications in 28
一款28 Gbs多标准串行链路收发器，适用于背板应用，采用28nm CMOS工艺，功耗低至295mW。
28nm CMOS, 1.25V, 295mW
JSSC 2015第12期RF & WirelessHigh-Speed Link
A 7 Gbs Embedded Clock Transceiver for Energy Proportional Links Tejasvi Anand S
提出一种支持快速开关的嵌入式时钟收发器，实现能效与通信量成正比。
65nm CMOS, 7Gb/s, 20ns锁定时间, 能效9.1pJ/bit至20.5pJ/bit
JSSC 2014第11期RF & WirelessHigh-Speed LinkEqualizer
An 816 Gbs 065105 pJb V oltage-Mode Transmitter With Analog Impedance Modulation
一种低功耗电压模式发射器，采用模拟阻抗调制技术，支持快速功率状态切换。
8-16 Gb/s, 0.65-1.05 pJ/b, 100-300 mV输出摆幅, 12 dB均衡
JSSC 2014第12期RF & WirelessHigh-Speed Link
A 1522 Gbps Serial Link in 28 nm CMOS With Direct DFE Vishnu Balan Member IEEE
28nm CMOS工艺下实现1522 Gbps半双工串行链路设计，支持20 dB损耗PCB信道。
28nm CMOS, 1.35V/0.9V, 20 Gbps, 6.5 mW/Gbps
JSSC 2013第3期RF & WirelessCDRHigh-Speed Link
A 25-Gbs 5-mW CMOS CDRDeserializer
一款采用电荷导向逻辑的低功耗25Gbps CDR解串器
1.5ps rms抖动, 0.5UI抖动容限@5MHz, 5mW功耗
JSSC 2013第11期RF & WirelessHigh-Speed LinkNeural Network Accelerator
A Low-Power 0566 Gbs Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs Jafar
一种嵌入低成本28nm FPGA的低功耗0.5-6.6 Gb/s自适应四通道收发器设计
28nm CMOS, 1.2V/1V, 6.6Gb/s, 20dB损耗通道BER<10^-12, 129mW
JSSC 2013第12期Wireline I/OHigh-Speed Link
A 054 pJb 20 Gbs Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm
28nm工艺下实现20Gb/s低功耗短距离单端串行链路，采用地参考信号技术。
28nm CMOS, 0.9V, 20Gb/s, 0.54pJ/bit, 4.5mm有机基板通道
JSSC 2012第4期RF & WirelessHigh-Speed LinkEqualizer
Power Optimized ADC-Based Serial Link Receiver
本文提出了一种基于ADC的低功耗串行链路接收器，采用非均匀参考电平和预均衡技术，在65nm CMOS工艺下实现10Gb/s数据传输。
65nm CMOS, 10Gb/s, 13pJ/bit (29dB信道), 10.6pJ/bit (23dB信道)
JSSC 2012第8期RF & WirelessHigh-Speed Link
016-025 pJbit 8 Gbs Near-Threshold Serial Link Receiver With Super-Harmonic Inje
提出一种近阈值电压的串行链路接收器，采用0.6V供电和超级谐波注入锁定技术实现低功耗。
65nm CMOS, 0.6V/1V, 8Gb/s, 0.163pJ/bit（无S/H）和0.25pJ/bit（带S/H）
JSSC 2012第12期RF & WirelessHigh-Speed LinkEqualizer
A 19-Gbs Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-
设计19Gb/s串行链路接收器，集成4抽头FFE和5抽头DFE功能。
45nm SOI CMOS, 0.07mm², 6.2mW/Gb/s
JSSC 2012第12期RF & WirelessHigh-Speed LinkEqualizer
A 28-Gbs 4-Tap FFE15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technolog
本文介绍了一种32nm SOI CMOS技术下的28Gb/s收发器，适用于高损耗电通道的芯片间通信。
28 Gb/s, 693 mW/lane, 35 dB loss at half-baud frequency
JSSC 2011第4期OtherHigh-Speed LinkEqualizer
A 625 Gbs V oltage-Time Conversion Based Fractionally Spaced Linear Receive Equa
提出基于电压-时间转换的分数间隔线性接收均衡技术，用于高速链路中的联合均衡与相位同步。
90nm CMOS, 1.2V, 6.25Gb/s, 3.6mW/Gb/s, >4bit线性度
JSSC 2011第11期Clocking & PLLsHigh-Speed Link
250 Mbps5 Gbps Wide-Range CDR With Digital V ernier Phase Shifting and Dual-Mode
提出一种采用数字游标移相和双模控制的宽范围CDR，支持250 Mbps至5 Gbps速率。
0.13μm CMOS, 1.2V, 5 Gbps, BER<10^-12
JSSC 2010第4期RF & WirelessVCOHigh-Speed Link
A 06 mWGbs 6472 Gbs Serial Link Receiver Using Local Injection-Locked Ring Oscil
本文提出了一种基于注入锁定环形振荡器的四通道6.4-7.2 Gb/s串行链路接收器，具有高能效和宽调谐范围。
6.4-7.2 Gb/s数据速率，BER<10^-12，0.6 mW/Gb/s能效
JSSC 2010第6期RF & WirelessHigh-Speed Link
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gbs Serial Links Ove
设计用于10Gbps串行链路的ADC前端，带数字校准功能
65nm CMOS, 1V, 500mW, 10Gbps
JSSC 2010第8期RF & WirelessCDRHigh-Speed Link
A 5 Gbps 013 22m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed
提出一种基于导频的时钟数据恢复技术，用于高速串行链路，具有低抖动和小面积优势。
0.13μm CMOS, 1.5V, 5Gbps, 10ps峰峰值抖动, 1.6ps RMS抖动, 28MHz CDR带宽
JSSC 2009第5期RF & WirelessCDRHigh-Speed Link
A Fully Integrated 013- 22m CMOS 40-Gbs Serial Link Transceiver Jeong-Kyoum Kim
本文介绍了一种基于0.13μm CMOS工艺的全集成40Gb/s串行链路收发器。
0.13μm CMOS, 1.45V, 40Gb/s, 3.6W, 3.4×2.9mm²
JSSC 2009第7期Clocking & PLLsHigh-Speed Link
A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock a
提出一种用于高速串行链路的稳健架构，满足1.5Gb/s和3Gb/s标准，采用最小化模拟功能和全数字设计。
90nm CMOS, 0.4mm², 75mW
JSSC 2007第5期RF & WirelessHigh-Speed Link
A Large-Swing Transformer-Boosted Serial Link Transmitter With 62866868Swing Jin
介绍了一种采用变压器升压技术的大摆幅串行链路发射器设计。
0.13μm CMOS, 1.2V, 8Gb/s, 1.42V差分输出摆幅, 137mA电流
JSSC 2007第9期RF & WirelessHigh-Speed Link
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme
一种用于移动显示器的低功耗单对串行链路，采用时钟边缘调制方案。
0.18μm CMOS, 1.2V, 270Mb/s, 3.12mW
JSSC 2006第3期Clocking & PLLsHigh-Speed LinkEqualizer
Cancellation of Crosstalk-Induced Jitter
提出一种新型抖动均衡电路，有效减少高速串行链路中的串扰诱导抖动。
5–10 Gb/s, 130-nm MOSFETs, 降低抖动从8.7到6.3 ps
JSSC 2006第4期RF & WirelessHigh-Speed Link
Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication
本文设计了一种无中继器的片上互连，采用脉冲电流模式信号传输，实现接近光速的延迟。
8-Gb/s 串行链路
JSSC 2006第6期RF & WirelessHigh-Speed LinkEqualizer
Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links
一种结合幅度预加重和相位预加重的新型均衡技术，用于低功耗串行链路，显著降低抖动和功耗。
6 Gb/s, 600 mVpp, 18 mW (无相位预加重), 24 mW (有相位预加重)
JSSC 2006第12期RF & WirelessHigh-Speed Link
A 995113-Gbs XFP Transceiver in 013-22m CMOS
一款用于XFP模块的9.95-11.3Gb/s收发器，采用0.13μm CMOS工艺，满足XFP抖动规范。
0.13μm CMOS, 9.95-11.3Gb/s, 800mW