子分类 · Wireline I/O

Equalizer

126 篇相关 JSSC 论文

JSSC 2025第1期MemoryEqualizerDRAM
A 16 Gb 37 Gb s GDDR7 DRAM With PAM3 Optimized TRX Equalization and ZQ Calibrat
一篇关于16Gb 37Gb/s GDDR7 DRAM的论文，重点介绍了PAM3优化的TRX均衡和ZQ校准技术。
16Gb, 37Gb/s
JSSC 2024第1期RF & WirelessHigh-Speed LinkEqualizer
A 112-Gbs Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for
一款支持112 Gb/s的多标准串行链路收发器，采用7nm FinFET工艺，功耗和面积效率高。
112 Gb/s, 43.9-dB IL补偿, 690-mW功耗, 0.63-mm²面积
JSSC 2024第1期RF & WirelessEqualizer
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gbs Wireline Receiver
28nm CMOS工艺下实现200Gb/s有线接收机的五抽头延迟线前馈均衡器
200Gb/s, 17.2dB损耗通道均衡, 0.42pJ/b能效
JSSC 2024第1期Power ManagementDLLEqualizer
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration Qiaoch
提出一种采用DTC控制注入时序的分数N数字MDLL，通过注入误差扰乱和校准技术降低杂散。
800-fs rms抖动, -67dBc分数杂散, -58dBc参考杂散
JSSC 2024第4期RF & WirelessEqualizer
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Referen
提出一种18Gb/s单端接收器，结合增益增强型有源电感CTLE和参考选择DFE，优化单端内存接口性能。
18Gb/s, -15dB信道损耗补偿, 0.14pJ/bit能效, 0.009pJ/bit/dB FoM
JSSC 2024第6期RF & WirelessCDREqualizer
A 10-Gbs Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for F
一种用于FSO-WDM系统的10Gbps有线接收器，采用线性波特率CDR和模拟均衡器。
3.8 pJ/bit, 0.147 mm²
JSSC 2024第7期RF & WirelessDACEqualizer
A 116-Gbs PAM4 09-pJb Transmitter With Eight-Tap FFE in 5-nm FinFET Yevgeny Pere
一篇关于116-Gb/s PAM4电压模式发射器的IEEE JSSC论文，采用5-nm FinFET工艺实现高效能传输。
116-Gb/s PAM4, 0.9 pJ/bit, 0.082 mm²面积
JSSC 2024第9期RF & WirelessVCOEqualizer
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based T
提出一种单端阻抗匹配发射器，采用环形振荡器时域ZQ校准，实现低误码率和高效能。
65nm CMOS, 12 Gb/s, 1.145 pJ/bit, FoM 0.11 pJ/bit/(dB/pin)
JSSC 2024第10期RF & WirelessEqualizerPAM-4
A 4 112 Gbs PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear
一款4×112 Gb/s硅光收发芯片组，用于线性驱动共封装光学应用。
180nm SiGe BiCMOS, 35GHz带宽, 112Gb/s PAM-4, 4.8pJ/bit(OTX), 2.95pJ/bit(ORX)
JSSC 2024第10期RF & WirelessDACEqualizer
A Fully Integrated QPSK16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband
一款基于28nm CMOS工艺的全集成D波段收发器，支持QPSK和16-QAM调制，具有混合信号基带处理能力。
28nm CMOS, 24-Gb/s QPSK, 48-Gb/s 16-QAM, TX带宽21 GHz, RX带宽18 GHz, TX Psat 13.1 dBm, TX OP 1 dB 7.5 dBm, RX NF 9.3 dB
JSSC 2023第1期RF & WirelessTime-Interleaved ADCEqualizer
A 141-pJb 224-Gbs PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable o
一篇关于在5纳米FinFET工艺中实现224Gb/s PAM4 ADC基SerDes接收器的论文
5nm FinFET, 224Gb/s, 1.41 pJ/b
JSSC 2023第1期RF & WirelessHigh-Speed LinkEqualizer
A 229-pJb 112-Gbs Wireline Transceiver With RX Four-Tap FFE for Medium-Reach App
一款用于中短距离电气链路的112Gb/s PAM-4收发器，采用RX四抽头FFE和两阶段16路交织技术。
28nm CMOS, 112Gb/s, BER<1e-11, 20.8dB信道损耗, 2.29pJ/b能效
JSSC 2023第10期RF & WirelessVCOEqualizer
A 103 fJbdB 1026 Gbs Receiver With a Dual Feedback Nested Loop CDR for Wide Band
提出一种高效能接收器，采用双反馈嵌套环CDR技术，提升高频抖动容限。
103 fJ/b/dB at 26 Gb/s
JSSC 2022第1期Wireline I/OEqualizerPAM-4
A 112-Gbs PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline R
本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。
112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b
JSSC 2022第1期RF & WirelessDACEqualizer
A 224-Gbs DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFE
一款基于DAC的224Gb/s PAM-4四分之一速率发射机，采用10nm FinFET工艺，具有8抽头FFE和低抖动时钟分布网络。
224Gb/s, 65fs rms随机抖动, 1.0Vppd输出摆幅, 1.88pJ/b能效
JSSC 2022第1期RF & WirelessEqualizer
A 56-Gbs 50-mW NRZ Receiver in 28-nm CMOS
28nm CMOS工艺下实现56Gbps低功耗NRZ接收器
56-Gb/s, BER<10^-12, 50-mW, 25dB信道损耗
JSSC 2022第1期Power ManagementEqualizer
Syn-STELLAR An EMPower SCA-Resilient AES-256 With Synthesis-Friendly Signature A
Syn-STELLAR提出了一种抗侧信道攻击的AES-256加密技术，通过数字友好的电流源和反馈机制提升安全性。
MTD从10M提升至250M
JSSC 2022第2期Digital CircuitsEqualizerNeural Network Accelerator
A 04-mA-Quiescent-Current 000091-THD N Class-D Audio Amplifier With Low-Complexit
提出一种低复杂度频率均衡技术，降低PWM残留混叠失真，实现低THD+N和低静态电流。
0.00091% THD+N, 0.0027% 最大THD+N, 168kHz fSW, 0.5-µm CMOS
JSSC 2022第3期RF & WirelessEqualizer
A Scalable 3256 Gbs 056128 pJb V oltage-Mode VCSEL-Based Optical Transmitter in
28nm CMOS工艺下实现56Gb/s能效1.28pJ/b的电压模式VCSEL光发射机
28nm CMOS, 1.15V, 56Gb/s NRZ, 1.28pJ/b
JSSC 2022第4期RF & WirelessEqualizerPAM-4
A 124-pJb 112-Gbs 870 GbsMm Transceiver for In-Package Links in 7-nm FinFET Chi
7nm FinFET工艺下1.24pJ/b能效的112Gb/s PAM4收发器芯片设计
1.24pJ/b能效, 112Gb/s速率, <1e-12误码率
JSSC 2022第4期RF & WirelessOptical I/OEqualizer
Silicon Photonic Microring-Based 4 112 Gbs WDM Transmitter With Photocurrent-Ba
本文介绍了一种基于微环调制器的4波长WDM光发射器，支持112 Gb/s速率，采用光电流热控制方案。
112 Gb/s, <0.7 dB TDECQ, 5.8 pJ/bit
JSSC 2022第5期RF & WirelessHigh-Speed LinkEqualizer
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Dom
提出一种采用PWM技术的PAM-8有线收发器，通过时间域前馈均衡提高线性度。
12.0至39.6 Gb/s，补偿14-dB损耗，6.6 GHz，8.66 pJ/bit效率
JSSC 2022第10期RF & WirelessEqualizerDRAM
A 21-Gbs Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer Do
提出一种用于GDDR接口的双二进制收发器，采用自适应均衡器技术，实现21Gb/s传输速率。
21 Gb/s, 1.42 mW/Gb, 10^-12误码率
JSSC 2022第10期RF & WirelessDACEqualizer
A 56-Gbs PAM-4 TransmitterReceiver Chipset With Nonlinear FFE for VCSEL-Based Op
一款56Gb/s PAM-4光链路收发芯片组，采用非线性FFE补偿VCSEL不对称响应。
56Gb/s, -0.9dBm OMA, 1.73pJ/b(TX), 4.96pJ/b(RX), BER<10^-12@0.08UI
JSSC 2021第2期RF & WirelessEqualizer
A Robust Efficient Distributed Power Amplifier Achieving 96 Gbits With 10 dBm Aver
基于互补增益级的伪差分分布式功率放大器，适用于5G室内通信，实现高带宽和高效率。
11.6 dB增益，0.4–31.6 GHz带宽，16.4 dBm峰值输出功率，17.2% PAE
JSSC 2021第3期RF & WirelessEqualizerPAM-4
A 60-Gbs PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization
一款采用2抽头直接判决反馈均衡的60Gbps PAM4有线接收器，具有低延迟和高能效特性。
28nm CMOS, 60 Gb/s, BER<1E-12, 1.1 pJ/b
JSSC 2021第7期RF & WirelessEqualizerPAM-4
A 112-Gbs PAM-4 V oltage-Mode Transmitter With Four-Tap Two-Step FFE and Automat
一款采用四抽头两步FFE和自动相位对齐技术的112Gbs PAM-4电压模式发射器
112 Gb/s, 3.89-pJ/b
JSSC 2021第8期Clocking & PLLsEqualizer
A 100-GSs Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS Hannes Ramon
55nm SiGe BiCMOS工艺实现的四合一100GS/s时间交织器，具有低时钟馈通和内置前馈均衡器。
55nm SiGe BiCMOS, 4.9 ENOB@3GHz, 73GHz带宽, 700mW功耗
JSSC 2021第8期Wireline I/OEqualizerDRAM
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Bas
提出一种用于高容量DRAM的控制器PHY，采用阻尼电阻辅助脉冲前馈均衡器减少信号干扰。
1067 Mb/s时C/A信号时序裕量从0.23 UI提升至0.29 UI，2133 Mb/s时DQ信号读写时序裕量分别为0.53 UI和0.72 UI
JSSC 2020第1期RF & WirelessEqualizerPAM-4
A 128-Gb-s 13-pJ-b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS
14nm CMOS FinFET技术实现的128Gb/s PAM-4发射机，具有可重构3抽头FFE和高效能设计。
128 Gb/s, 1.33 pJ/b, 1-V ppd输出幅度
JSSC 2020第1期RF & WirelessEqualizer
A 161-mW 56-Gb-s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-
14nm FinFET工艺下，实现56Gb/s速率、161mW功耗的DMT接收器数据路径。
56 Gb/s, 161 mW, 1.2 pJ/b (DSP), 2.9 pJ/b (RX), BER < 2e-4
JSSC 2020第3期RF & WirelessSAR ADCTDC
A 128-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer
本文展示了一种基于ADC的接收器，支持NRZ/PAM4调制，集成了IIR均衡器，采用65nm CMOS工艺，能效为2.43-pJ/b。
65nm CMOS, 12.8-Gbaud PAM4, 2.43-pJ/b, 4.84 peak ENOB, 36.3 mW, 0.24 mm²
JSSC 2020第3期Wireline I/OEqualizer
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication-Dicode
提出一种无需均衡器的ISI弹性Dicode编码方案，用于低带宽有线通信。
65-nm CMOS, 2.56-2.66 pJ/bit, 13.6-16 Gb/s, BER < 10^-12
JSSC 2020第4期RF & WirelessTime-Interleaved ADCEqualizer
112-Gb-s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channel
采用10nm FinFET工艺实现的112Gb/s PAM4 ADC基SERDES接收器，支持长距离通信。
112Gb/s, -35dB Nyquist通道, 1e-6预FEC BER
JSSC 2020第7期RF & WirelessEqualizerPAM-4
A 50-112-Gb-s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
65nm CMOS工艺下实现50-112Gb/s PAM-4发射机，采用分数间隔FFE提升眼图性能
112Gb/s最高数据速率，2.17pJ/bit能效
JSSC 2020第7期RF & WirelessHigh-Speed LinkEqualizer
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for C
提出一种基于时钟域编码的iPWM线编码方案，实现低电压下的高效均衡。
3–16 Gb/s, 0.5-0.9V, 27dB channel loss, 1.8 pJ/bit
JSSC 2020第7期Analog CircuitsEqualizer
Analog I-Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at
提出一种用于16-QAM光通信的55nm SiGe BiCMOS模拟I-Q FIR滤波器，补偿频率相关变化。
55nm BiCMOS, 185mW核心功耗, 112Gb/s 16-QAM调制信号
JSSC 2020第8期RF & WirelessEqualizer
A 01-pJbdB 162-to-108-Gbs Video Interface Receiver With Jointly Adaptive CTLE an
一款采用联合自适应均衡技术的1.62至10.8 Gb/s视频接口接收器，通过SSLMS算法优化CTLE和DFE，实现高效能和低功耗。
65nm CMOS, 37.2 mW at 10.8 Gb/s, 0.1 pJ/b/dB
JSSC 2020第8期RF & WirelessCDREqualizer
A 12-Gbs 10-ns Turn-On Time Rapid ONOFF Baud-Rate DFE Receiver in 65-nm CMOS
一款65nm CMOS工艺的12Gbps快速启停接收器，支持10ns启动时间
12 Gb/s, BER < 10^-12, >30-MHz JTOL corner, 377 fs rms jitter, 3.8-pJ/bit
JSSC 2019第1期RF & WirelessEqualizerPAM-4
A 112 Gbps PAM-4 56 Gbps NRZ Reconfigurable Transmitter With Three-Tap FFE in 10
一款采用10nm FinFET工艺的可重构发射器，支持112 Gbps PAM-4和56 Gbps NRZ调制。
112 Gb/s PAM-4调制下功耗232 mW，能效2.07 pJ/b
JSSC 2019第1期RF & WirelessPLLEqualizer
A 16-Gb 18-Gbps per pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and P
16Gb GDDR6 DRAM采用每比特可训练单端DFE和ZQ编码发射器，实现18Gbps/pin高速操作
16 Gb/s/pin @1.15V, 18 Gb/s/pin @1.35V
JSSC 2019第1期RF & WirelessEqualizerPAM-4
A 64 Gbps Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm
28nm FDSOI工艺下64Gbps低功耗PAM-4收发器，支持短距电气链路。
28nm CMOS, 1V供电, 64Gbps速率, 2.8mW/Gb/s能效, 10^-12误码率
JSSC 2019第1期RF & WirelessSAR ADCHigh-Speed Link
A Fully Adaptive 1958-Gbps PAM-4 and 9529-Gbps NRZ Wireline Transceiver With Con
一款16nm FinFET工艺的双模PAM-4/NRZ收发器，支持19-58Gb/s PAM-4和9.5-29Gb/s NRZ传输。
16nm FinFET, <1e-12 BER, 9.7 pJ/bit
JSSC 2019第2期RF & WirelessEqualizer
A 64-Gbps 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET
16nm FinFET工艺的64Gbps 4-PAM收发器，采用自适应阈值ADC优化功耗与误码率。
16nm FinFET, 1.2V, 64Gbps, 1.39pJ/bit, BER<1e-6
JSSC 2019第2期Wireline I/OEqualizerSRAM
A 7T-SRAM With Data-Write Technique by Capacitive Coupling
提出一种通过电容耦合写入数据的7T-SRAM，解决电流冲突问题并提升稳定性。
24nm 3.3V CMOS, 1.5V/1.8V Vdd, 20ns/10ns cycle time, 18ns/10ns access time, 400 FIT/Mb SER
JSSC 2019第3期RF & WirelessEqualizerPAM-4
A 52-Gbps ADC-Based PAM-4 Receiver
一款基于ADC的PAM-4接收器，采用32路时间交织SAR ADC和数字均衡技术，实现52Gbps高速数据传输。
52-Gbps数据传输速率，BER<10−6（31dB损耗信道）
JSSC 2019第3期RF & WirelessEqualizerPAM-4
A 56-Gbps PAM4 Receiver With Low-Overhead Techniques
本文介绍了一种56-Gbps PAM4接收器，采用低开销技术有效补偿信道损耗。
56-Gb/s, 4.63 mW/Gb/s, BER < 10^-12
JSSC 2019第10期RF & WirelessEqualizer
A2 Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infin
提出一种结合自适应均衡和时序恢复的盲过采样FSE接收器，支持准同步时钟。
28nm CMOS, 3.5 pJ/bit, 0.10 mm², 9 Gb/s, 22-dB信道损耗补偿, 100ppm频率偏移
JSSC 2019第10期Clocking & PLLsEqualizer
DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling Masum Hossai
一种低延迟低功耗的双模NRZ和PAM-4时序恢复电路，直接自适应均衡DDJ。
65nm CMOS, 10-Gb/s NRZ, 20-Gb/s PAM-4, 23 mW, >20 MHz跟踪带宽
JSSC 2018第1期RF & WirelessEqualizer
A Time Based Receiver With 2 Tap Decision Feedback Equalizer for Single Ended M
提出一种基于时间的接收器，采用2抽头判决反馈均衡器，适用于单端M接口。
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JSSC 2018第3期OtherEqualizer
An Eight Lane 7 Gbspin Source Synchronous Single Ended RX With Equalization and
一款八通道7Gbps源同步单端接收器，具备均衡功能。
7Gbps, 单端接收, 均衡功能
JSSC 2017第12期RF & WirelessEqualizer
A 40 to 56 Gbs PAM 4 Receiver With Ten Tap Direct Decision Feedback Equalizatio
一篇关于40至56 Gbs PAM4接收器设计，采用十抽头直接决策反馈均衡技术的IEEE JSSC论文。
40至56 Gbs数据传输速率
JSSC 2016第8期OtherEqualizer
A Modelling and Nonlinear Equalization Technique for a 20 Gbs 077 pJb VCSEL Tra
一篇关于20 Gbps VCSEL非线性均衡技术的IEEE JSSC论文
20 Gbps, 077 pJb
JSSC 2015第2期RF & WirelessHigh-Speed LinkEqualizer
425 Gbs Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Tech
本文介绍了一种用于100 GbE系统的4×25 Gb/s全集成收发器芯片组，采用65 nm CMOS工艺。
65 nm CMOS, 4×25 Gb/s, 100 GbE标准
JSSC 2015第2期RF & WirelessEqualizer
A 25 Gbs 58 mW CMOS Equalizer
一款采用45nm工艺的低功耗25Gbps CMOS均衡器设计
25Gbps, 58mW, 1V供电, 24dB损耗补偿
JSSC 2015第4期RF & WirelessHigh-Speed LinkEqualizer
A 40 Gbs Serial Link Transceiver in 28 nm CMOS Technology Reza Navid Senior Mem
本文介绍了一种40 Gb/s的串行链路收发器，采用28 nm CMOS工艺，优化了芯片间通信并补偿20 dB信道损耗。
28nm CMOS, 40 Gb/s, 23.2 mW/Gb/s, 0.27 UI水平眼图开口, 120 mV垂直眼图开口
JSSC 2015第7期Wireline I/OEqualizer
A 041 pJBit 10 Gbs Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS Sha
提出一种混合IIR和离散时间DFE的10Gb/s低功耗接收器设计。
28nm CMOS, 150mVpp-diff, 10Gb/s, 4.1mW, 24dB信道损耗
JSSC 2015第7期RF & WirelessEqualizer
An Evolved GSMEDGE Baseband ASIC Supporting Rx Diversity Harald Kröll Student Me
支持接收分集的GSM/EDGE基带ASIC，满足3GPP最严苛的下行链路性能要求。
130nm CMOS, 3.9-14mW功耗, 112dBm灵敏度
JSSC 2015第8期RF & WirelessEqualizer
A 14 pJbit Power-Scalable 1612 Gbs Source-Synchronous IO With DFE Receiver in 32
一款功率可扩展的14 pJbit 1612 Gbs源同步IO，采用DFE接收器，32nm SOI CMOS工艺。
12 Gb/s每通道，1.4 pJ/b效率（0.75英寸Megtron-6 PCB），1.9 pJ/b效率（20英寸Megtron-6 PCB）
JSSC 2015第11期RF & WirelessEqualizerDRAM
A 168 GbpsChannel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Inte
提出一种65nm CMOS工艺的16.8 Gbps单端收发器，用于SiP基DRAM接口。
65 nm CMOS, 16.8 Gbps, BER < 1e-12, 5.9 pJ/bit
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