子分类 · Wireline I/O

PAM-4

64 篇相关 JSSC 论文

JSSC 2025第10期RF & WirelessPAM-4
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS
本文提出了一种56Gb/s PAM-4 VCSEL发射器，采用分段补偿方案解决VCSEL的非理想特性。
56-Gb/s PAM-4, 2.05 pJ/b
JSSC 2025第11期RF & WirelessPAM-4
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS
本文提出了一种用于VCSEL的四电平脉冲幅度调制发射机，采用分段补偿方案解决非线性问题。
56-Gb/s PAM-4, 2.05 pJ/b
JSSC 2024第1期RF & WirelessPAM-4
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and
4纳米CMOS工艺下16Gbps单端PAM-4收发器，采用切换抖动补偿技术提升时序裕度
16-Gb/s/pin, 0.764-pJ/b
JSSC 2024第2期RF & WirelessCDRPAM-4
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
一款60Gbs PAM-4接收器，采用抖动补偿CDR技术，实现低抖动传输与高带宽容忍。
40nm CMOS, 30-60Gb/s, <-8dB JTRAN, 40MHz JTOL带宽, 60%抖动补偿率
JSSC 2024第5期RF & WirelessPAM-4
A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for
首款低温CMOS 40-Gb/s PAM4有线发射器，用于量子计算数据传输。
40nm CMOS, 40-Gb/s (36-Gb/s), 2.46 pJ/b (2.47 pJ/b), 97.8% (96.6%) RLM
JSSC 2024第5期Wireline I/OPAM-4
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS
28nm CMOS工艺下设计的非相干100Gbps双波段PAM-4塑料光纤链路
28nm CMOS, 100Gb/s@3m, 574mW, BER<2.2e-4
JSSC 2024第7期RF & WirelessDACEqualizer
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET Yevgeny Perelman , Zeev Toroker , Daljeet Kumar , Eran Maday, Noam Familia
一篇关于116-Gb/s PAM4电压模式发射器的IEEE JSSC论文，采用5-nm FinFET工艺实现高效能传输。
116-Gb/s PAM4, 0.9 pJ/bit, 0.082 mm²面积
JSSC 2024第7期RF & WirelessPAM-4
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET
12nm CMOS FinFET工艺下的低功耗高带宽PAM4 VCSEL驱动器，支持64Gb/s数据传输。
12nm CMOS, 1/2/-1.5V, 50Gb/s NRZ, 64Gb/s PAM4, 0.82pJ/b
JSSC 2024第8期RF & WirelessHigh-Speed LinkPAM-4
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4
一种采用共模NRZ和差分PAM-4混合信号实现3比特/符号传输的线缆收发器。
28nm CMOS, 48 Gb/s, 0.117 mm², BER 10⁻¹² at 9.0
JSSC 2024第9期RF & WirelessPAM-4Neural Network Accelerator
A 2 × 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
一种基于主动串扰消除的2×56 Gb/s PAM-4接收器，能效达0.78 pJ/b。
56 Gb/s PAM-4, BER <1e-10, 24-dB Nyquist loss, 0.78 pJ/b/lane
JSSC 2024第10期RF & WirelessEqualizerPAM-4
A 4 × 112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics
一款4×112 Gb/s硅光收发芯片组，用于线性驱动共封装光学应用。
180nm SiGe BiCMOS, 35GHz带宽, 112Gb/s PAM-4, 4.8pJ/bit(OTX), 2.95pJ/bit(ORX)
JSSC 2024第10期RF & WirelessPAM-4DRAM
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed
提出一种采用PAM-4调制、数据总线反转和ZQ校准的单端DRAM接口发射机设计，提升能效并降低噪声。
38 Gb/s, 26.16 mW, 0.688 pJ/bit
JSSC 2023第1期RF & WirelessOptical I/OPAM-4
A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP
3D集成的硅光子-CMOS平台实现100Gbps PAM4光发射机
28nm CMOS, 0.9V, 100Gbps, 240mW, 2.4pJ/bit
JSSC 2023第1期RF & WirelessTime-Interleaved ADCEqualizer
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels Ahmad Khairi , Y
一篇关于在5纳米FinFET工艺中实现224Gb/s PAM4 ADC基SerDes接收器的论文
5nm FinFET, 224Gb/s, 1.41 pJ/b
JSSC 2023第1期RF & WirelessHigh-Speed LinkEqualizer
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS Bingyi Y e
一款用于中短距离电气链路的112Gb/s PAM-4收发器，采用RX四抽头FFE和两阶段16路交织技术。
28nm CMOS, 112Gb/s, BER<1e-11, 20.8dB信道损耗, 2.29pJ/b能效
JSSC 2023第5期RF & WirelessCDRPAM-4
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
提出一种48 Gb/s PAM-4接收器，采用可调预游标的波特率相位检测器，优化垂直眼图开口。
48 Gb/s, BER < 10^-11, 2.42 pJ/b
JSSC 2023第7期RF & WirelessPAM-4
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces Y
一种25Gb/s单端PAM-4接收器，采用时间窗LSB解码器，提升高速内存接口能效。
28nm CMOS, 0.008mm², 0.34pJ/bit@25Gb/s
JSSC 2022第1期RF & WirelessPAM-4
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS
一款集成2抽头FFE和2抽头直接反馈DFE的100Gbps PAM-4光接收器
28nm CMOS, 100Gb/s, -8.9dBm灵敏度@2.4e-4 BER, 3.9pJ/bit能效
JSSC 2022第1期Wireline I/OEqualizerPAM-4
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET
本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。
112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b
JSSC 2022第1期RF & WirelessDACEqualizer
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
一款基于DAC的224Gb/s PAM-4四分之一速率发射机，采用10nm FinFET工艺，具有8抽头FFE和低抖动时钟分布网络。
224Gb/s, 65fs rms随机抖动, 1.0Vppd输出摆幅, 1.88pJ/b能效
JSSC 2022第1期Wireline I/OPAM-4DRAM
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido
通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。
22 Gbps per-pin data rate
JSSC 2022第1期RF & WirelessPAM-4
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS Zhongkai Wang , Associate Member , IEEE
28nm CMOS工艺下实现200Gb/s PAM-4和100Gb/s NRZ的发射机，优化带宽和摆幅
28nm CMOS, 200Gb/s PAM-4, 100Gb/s NRZ, >52.9mV眼高, 0.36UI眼宽, >98% RLM, 4.63pJ/b
JSSC 2022第2期Clocking & PLLsCDRPAM-4
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Re ference and Separate FD Pulling Off an 8.2-Gb/s/ μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS
本文提出了一种无需参考和独立频率检测器的单环路全速率Bang-Bang时钟数据恢复电路，支持PAM-4模式，具有宽频率捕获范围和高能效。
28nm CMOS, 23-to-29-Gb/s capture range, 0.68 pJ/bit energy efficiency
JSSC 2022第2期RF & WirelessPAM-4
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator V oltage V ariations
28nm CMOS工艺下采用时间域LSB解码器和S/H技术的56Gb/s PAM-4接收器
28nm CMOS, 56Gb/s, 0.975pJ/bit
JSSC 2022第3期RF & WirelessPAM-4
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR
一款50Gb/s PAM-4硅光发射器，采用集总段MZM设计，实现高带宽和线性调制。
50Gb/s, 9.8dB ER, 0.99 level mismatch ratio, 1.39pJ/bit/dB FoM, 682mW power
JSSC 2022第4期RF & WirelessEqualizerPAM-4
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET Chi Fung Poon , Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Daniel Zhaoyin Wu, Kee Hian Tan
7nm FinFET工艺下1.24pJ/b能效的112Gb/s PAM4收发器芯片设计
1.24pJ/b能效, 112Gb/s速率, <1e-12误码率
JSSC 2022第5期Wireline I/OPAM-4Neural Network Accelerator
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS
22nm FinFET CMOS工艺下实现的高能效128Gb/s单端PAM4线性TIA
22nm FinFET CMOS, 0.8V, 128Gb/s PAM4, 59.3dBΩ增益, 11.2mW功耗, 45.5GHz带宽, 27μArms输入噪声
JSSC 2022第5期Clocking & PLLsCDRPAM-4
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems Takashi Toi
提出一种基于PAM-4的四通道复用和级联CDR的256Gb/s接口，用于高带宽大容量NAND闪存系统。
28nm CMOS, 3.69pJ/b能效, 25.6Gb/s速率, BER<1e-15, 1.84dB损耗
JSSC 2022第5期Clocking & PLLsCDRPAM-4
A Sub-0.25-pJ/bit 47.6-to- 58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Xiaoteng Zhao , Student Member , IEEE
一种无需参考和频率检测器的半速率单环路Bang-Bang时钟数据恢复电路，实现高速低功耗PAM-4信号处理。
28nm CMOS, 0.056mm²核心面积, 0.22–0.25 pJ/bit能效, 9.8 (Gb/s)/µs捕获速度
JSSC 2022第6期RF & WirelessPLLPAM-4
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for
提出一种采用耦合倍频器的低相位噪声数字LC-PLL，用于224Gb/s PAM-4发射机时钟
23.9-29.4GHz, 65fs随机抖动, 17.1mW功耗, 0.8/1.0V供电
JSSC 2022第9期RF & WirelessCDRPAM-4
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High
一种低功耗PAM4 CDRDMUX电路，具有高抖动容限和宽环路带宽。
56 Gbps, 8 mW, 160 MHz抖动传输带宽, 1 UI抖动容限@10 MHz
JSSC 2022第10期RF & WirelessDACEqualizer
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS
一款56Gb/s PAM-4光链路收发芯片组，采用非线性FFE补偿VCSEL不对称响应。
56Gb/s, -0.9dBm OMA, 1.73pJ/b(TX), 4.96pJ/b(RX), BER<10^-12@0.08UI
JSSC 2022第10期Clocking & PLLsCDRPAM-4
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic
提出一种基于随机相位检测器的48Gb/s PAM-4波特率CDR设计技术
48 Gb/s, 24 pJ/b, BER<10^-11, 0.24 mm^2
JSSC 2021第1期RF & WirelessSAR ADCHigh-Speed Link
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
7nm FinFET CMOS工艺下实现的112Gb/s PAM-4长距离有线收发器
112Gb/s PAM-4, <1E-8 PRBS-31 BER, 37.5dB损耗@28GHz, 602mW/通道
JSSC 2021第1期RF & WirelessOptical I/OEqualizer
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and
3D集成的硅光子微环112Gbs PAM-4发射器，具有热控制和非线性均衡功能。
112 Gb/s, TDECQ <1.5 dB, 7.4-pJ/bit能效
JSSC 2021第3期RF & WirelessEqualizerPAM-4
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS
一款采用2抽头直接判决反馈均衡的60Gbps PAM4有线接收器，具有低延迟和高能效特性。
28nm CMOS, 60 Gb/s, BER<1E-12, 1.1 pJ/b
JSSC 2021第4期RF & WirelessPAM-4
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single- Ended PAM-4 Transmitter With an Impedance- Matched Driver and Three-Point ZQ Calibration for Memory Interface Y
一款高线性度单端PAM-4发射器，通过阻抗匹配和三端ZQ校准实现28Gbps/pin传输
65nm CMOS, 0.0333mm², 0.64pJ/bit, 28Gb/s/pin
JSSC 2021第7期RF & WirelessEqualizerPAM-4
A 112-Gb/s PAM-4 V oltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS
一款采用四抽头两步FFE和自动相位对齐技术的112Gbs PAM-4电压模式发射器
112 Gb/s, 3.89-pJ/b
JSSC 2020第1期RF & WirelessEqualizerPAM-4
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS
14nm CMOS FinFET技术实现的128Gb/s PAM-4发射机，具有可重构3抽头FFE和高效能设计。
128 Gb/s, 1.33 pJ/b, 1-V ppd输出幅度
JSSC 2020第1期RF & WirelessDACPAM-4
A 243-mW 1.25–56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET
一款基于ADC-DAC的7nm FinFET技术收发器，支持3.5-56 Gb/s PAM-4，功耗仅243mW。
56 Gb/s PAM-4, 243 mW, 4.3 pJ/b
JSSC 2020第3期RF & WirelessSAR ADCTDC
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer Jae-Won Nam , Student Member , IEEE, and Mike
本文展示了一种基于ADC的接收器，支持NRZ/PAM4调制，集成了IIR均衡器，采用65nm CMOS工艺，能效为2.43-pJ/b。
65nm CMOS, 12.8-Gbaud PAM4, 2.43-pJ/b, 4.84 peak ENOB, 36.3 mW, 0.24 mm²
JSSC 2020第3期RF & WirelessPLLPAM-4
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS
一款14GHz Bang-Bang数字PLL，集成抖动低于150fs，用于高速有线通信。
14GHz, 143-fs rms抖动, 56-Gb/s PAM-4, 40mW功耗
JSSC 2020第4期RF & WirelessTime-Interleaved ADCEqualizer
112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels Y
采用10nm FinFET工艺实现的112Gb/s PAM4 ADC基SERDES接收器，支持长距离通信。
112Gb/s, -35dB Nyquist通道, 1e-6预FEC BER
JSSC 2020第4期RF & WirelessPAM-4
Errata Erratum to “A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS”
关于论文作者照片错误的更正声明
无
JSSC 2020第5期RF & WirelessOptical I/OPAM-4
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS Qiwen Liao ,N a nQ i , Member , IEEE, Miaofeng Li, Shang Hu , Jian He, Bozhi Yin, Jingbo Shi , Jian Liu , Patrick
一款50Gb/s PAM4硅光发射器，采用数字辅助分布式驱动器和混合集成技术。
50Gb/s PAM4, 40nm CMOS, 180nm SOI CMOS
JSSC 2020第7期RF & WirelessEqualizerPAM-4
A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
65nm CMOS工艺下实现50-112Gb/s PAM-4发射机，采用分数间隔FFE提升眼图性能
112Gb/s最高数据速率，2.17pJ/bit能效
JSSC 2020第8期RF & WirelessPAM-4
A 25Gbaud PAM-4 Linear Burst-Mode Receiver With Analog Gain- and Offset Control in 0.25μm SiGe:C BiCMOS
一款支持25Gbaud PAM-4调制的线性突发模式接收器，具有模拟增益和偏移控制功能
25Gbaud NRZ: -18.1dBm灵敏度, 3.5dBm过载; PAM-4: -11.4dBm灵敏度, 4.4dBm过载; 280mW功耗
JSSC 2020第10期Clocking & PLLsPLLCDR
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase
本文提出了一种四电平脉冲幅度调制(PAM4)四分之一速率时钟和数据恢复电路(CDR)，采用线性相位检测器和自偏置PLL多相时钟发生器，实现了低功耗和低抖动。
40nm CMOS, 32-Gb/s, 0.46 pJ/bit, 352.6 fs抖动
JSSC 2019第1期RF & WirelessEqualizerPAM-4
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET
一款采用10nm FinFET工艺的可重构发射器，支持112 Gbps PAM-4和56 Gbps NRZ调制。
112 Gb/s PAM-4调制下功耗232 mW，能效2.07 pJ/b
JSSC 2019第1期RF & WirelessEqualizerPAM-4
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS Emanuele Depaoli , Hongyang Zhang, Marco Mazzini, Walter Audoglio, Augusto Andrea Rossi
28nm FDSOI工艺下64Gbps低功耗PAM-4收发器，支持短距电气链路。
28nm CMOS, 1V供电, 64Gbps速率, 2.8mW/Gb/s能效, 10^-12误码率
JSSC 2019第1期RF & WirelessSAR ADCHigh-Speed Link
A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET
一款16nm FinFET工艺的双模PAM-4/NRZ收发器，支持19-58Gb/s PAM-4和9.5-29Gb/s NRZ传输。
16nm FinFET, <1e-12 BER, 9.7 pJ/bit
JSSC 2019第1期RF & WirelessPAM-4
JANUARY 2019 VOLUME 54 NUMBER 1 IJSCBC (ISSN 0018-9200) SPECIAL ISSUE ON THE 2018 INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
IEEE JSSC期刊论文摘要，涵盖多篇关于高速低功耗收发器的研究。
64 Gb/s, 19-58 Gb/s, 112 Gb/s
JSSC 2019第3期RF & WirelessSAR ADCEqualizer
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS
一款基于ADC的PAM-4接收器，采用32路时间交织SAR ADC和数字均衡技术，实现52Gbps高速数据传输。
52-Gbps数据传输速率，BER<10−6（31dB损耗信道）
JSSC 2019第3期RF & WirelessEqualizerPAM-4
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
本文介绍了一种56-Gbps PAM4接收器，采用低开销技术有效补偿信道损耗。
56-Gb/s, 4.63 mW/Gb/s, BER < 10^-12
JSSC 2019第6期RF & WirelessPAM-4
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for
一款支持数字预失真PAM-4调制的127 GHz毫米波CMOS收发器，用于非接触通信。
20 Gb/s, 1.2V, 79.5 mW, 3.98-pJ/bit
JSSC 2019第10期RF & WirelessPAM-4Neural Network Accelerator
A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and
提出一种支持PAM4/NRZ的多模收发器，具有自适应功耗CDR和抖动分析功能
28nm CMOS, 0.25-27Gb/s, 3.8pJ/bit (TX), 6.2pJ/bit (RX)
JSSC 2019第11期Wireline I/OPAM-4Neural Network Accelerator
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ λ PAM-4
一款16nm FinFET CMOS工艺的线性TIA，支持100Gbs PAM-4光链路，具有高带宽、低噪声和低功耗特性。
16nm FinFET CMOS, 60.8mW功耗, 27GHz带宽, 16.7pA/√Hz输入噪声密度
JSSC 2018第8期RF & WirelessPAM-4
An 80 Gbs 44 mW Wireline PAM4 Transmitter
一款80 Gbps、44 mW的PAM4有线发射器
80 Gbps, 44 mW
JSSC 2017第4期RF & WirelessSAR ADCHigh-Speed Link
A 56 Gbs PAM4 Wireline Transceiver Using a 32 Way Time Interleaved SAR ADC in 1
本文介绍了一种采用32路时间交织SAR ADC的56 Gbps PAM4有线收发器。
56 Gbps, 32-way time-interleaved SAR ADC
JSSC 2017第9期Wireline I/OPAM-4
A Reconfigurable 16 32 Gb s Dual Mode NRZ PAM4 SerDes in 65 nm CMOS
一篇关于在65纳米CMOS工艺中实现可重构16/32 Gb/s双模式NRZ/PAM4 SerDes的论文
16/32 Gb/s, 65nm CMOS
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