A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

📋 论文概要

该论文提出了一种采用4nm工艺的32Gb/s 8Tb/s/mm die-to-die芯片间互连方案，使用NRZ单端收发器并集成均衡方案和训练技术，解决了高带宽密度、低功耗的芯片间通信问题。

💡 主要创新点

• 采用NRZ单端收发器实现高带宽密度，达到8Tb/s/mm。
• 集成均衡方案和训练技术，提升信号完整性并降低误码率。

🏷 关键词

📄 原文摘要

Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwasung, Korea Recently, the demand for multi-chip solutions, such as chip-on-wafer-on-substrate (CoWoS) and embedded multi-die interconnect bridge (EMIB), is increasing as they reduce chip size and cost for high-performance computing (HPC), artificial intelligence (AI), and big data applications [1]. Following this trend, the industry is establishing standard specifications for die-to-die interfaces, such as Universal Chiplet Interconnet Express (UCIe) and Open High-Bandwidth Interface (OpenHBI), and developing various chiplets with high data transmission bandwidth per unit width, low latency, and low power consumption [2-5]. This work implements a die-to-die (D2D) chiplet compatible with the UCIe specification using 2.5D packaging technology for die-to-die

👥 作者与机构

Kihwan Seong, Donguk Park, Gyeomje Bae, Hyunwoo Lee, Youngseob Suh,