ISSCC 2023Session 6 · ADVANCED WIRELINE LINKS AND TECHNIQUESWireline I/O

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET detection can either use a low-latency short FFE to minimize peaking in the jitter transfer curve or use the main FFE/DFE output for very high loss channels (> 40dB).

⚡ 本页包含 AI 生成的分析内容，仅供参考

📋 论文概要

论文提出了一种基于DSP的112Gb/s PAM-4收发器，采用5nm FinFET工艺，实现了4.63pJ/b的能效。针对ADC采样保持开关线性度问题，提出了自适应共模偏置技术以提升接收性能。

发表年份

ISSCC 2023

📄 原文摘要

Qaiser Nehal1, Miguel Gandara1, Tsz-Bin Liu2, Amr Khashaba1, Joonyeong Lee1, Chih-Yi Kuan2, Dhinessh Ramachandran1, Ruey-Bo Sun2, Atharav Atharav1, Yusang Chun1, Mantian Zhang1, Deng-Fu Weng2, Chung-Hsien Tsai2, Chen-Hao Chang2, Chia-Sheng Peng2, Sheng-Tsung Hsu2, Tamer Ali1 The unit 7b ADC (1GS/s) and its S/H switch can resolve 400mVppd signal swing. Since the core devices operate under 0.75V supply, the ADC S/H switch linearity may limit RX performance due to either settling error or leakage. An efficient way to improve the ADC S/H switch linearity is by adaptive common-mode (CM) biasing. A slow corner device favors a high CM level as the switch leakage is inherently small, while a fast corner device can benefit from a low CM level (Fig. 6.2.3(b)). Figure 6.2.3(c) shows an ADC input CM generation circuit for a PVT-insensitive S/H switch performance. This circuit generates a minimum tolerable input voltage of a replica S/H switch (VSH_MIN) with a target

👥 作者与机构

Henry Park*1, Mohammed Abdullatif*1, Ehung Chen1, Ahmed Elmallah1,

分类：Wireline I/O · 年份：ISSCC 2023