A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard Package

📋 论文概要

该论文提出了一种符合UCIe-S标准的die-to-die物理层，在16通道上实现48Gb/s/lane速率，在30mm有机封装上达到1.24Tb/s/mm的岸线带宽密度和1.2pJ/b能效。通过阻抗不变TX CTLE、高摆幅N/N驱动器、紧凑谐振时钟、改进的双尾锁存器等电路创新，相比先前UCIe-S实现了3倍数据率和2.8倍带宽密度提升。

💡 主要创新点

• 阻抗不变的发射机连续时间线性均衡器（TX CTLE），在保持阻抗匹配的同时实现均衡。
• 高摆幅N/N驱动器，提高了输出电压摆幅并降低功耗。
• 紧凑谐振时钟分配和双尾锁存器改善建立/保持时间，以及共模电源噪声抑制技术。

🏷 关键词

📄 原文摘要

work demonstrates a UCIe-S compliant die-to-die PHY at 48Gb/s/lane across 16 lanes, achieving 1.24Tb/s/mm shoreline BW density over a 30mm organic package at 1.2pJ/b, extendable to 56GT/s (1.13pJ/b). Circuit innovations include an impedance-invariant TX CTLE, high-swing N/N driver, compact resonant clocking, double-tail latch w/ improved setup/hold times, and common-mode supply-noise rejection. Compared to prior UCIe-S, it achieves 3× higher data rate and 2.8× higher BW density. As system complexity grows, monolithic SoC scaling faces challenges in integration, die size, and technology heterogeneity, motivating chiplet disaggregation that improves yield and cost while enabling IP reuse and heterogeneous integration. Die-to-die (D2D) interconnects with low latency, high bandwidth (BW) density and energy efficiency (EE) are

👥 作者与机构

Susnata Mondal*1, Sashank Krishnamurthy*1, Shuhei Yamada1, Zhaokai Liu2, Junyi Qiu1, Soumya Bose3, Zuoguo Wu2, Gerald Pasdast2, James Jaussi1, Mozhgan Mansuri1

Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3University of California, Santa Cruz, CA *Equally Credited Authors (ECAs) 1 Abstract This