A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur

📋 论文概要

本文提出了一种基于环形振荡器的乒乓采样PLL，在0.027mm²面积内实现了5.6-7.8GHz频率范围，220.2fsrms的抖动和-74.2dBc的参考杂散，解决了环形振荡器相位噪声和闪烁噪声问题，适合多通道通信应用。

💡 主要创新点

• 提出乒乓采样技术降低环形振荡器PLL的相位噪声和闪烁噪声。
• 实现了极小面积（0.027mm²）和宽频率调谐范围的环形振荡器PLL。
• 在5.6-7.8GHz频段达到低抖动和低参考杂散的优异性能。

🏷 关键词

📄 原文摘要

Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A ring oscillator (RO) based phase-locked loop (PLL) is a promising candidate for multilane communication applications due to its small footprint, wide frequency tuning range, inherent multi-phase generation and frequency-pulling resilience. However, the RO suffers from inferior phase noise (PN) and a high flicker-noise corner, limiting the overall jitter performance. While the injection-locked clock multiplier (ILCM) [1] and the multiplying delay-locked loop (MDLL) [2] can effectively suppress the RO PN through the phase-realignment mechanism, the reference (REF) spur increases significantly due to the imperfect alignment timing, thus imposing a complex calibration. Type-I topology with a sampling phase detector or filter is attractive due to the inherent stability under

👥 作者与机构

Yunbo Huang1, Yong Chen1, Zunsong Yang2, Rui P. Martins1,3, Pui-In Mak1

University of Macau, Macau, China