A 2×500Gb/s Monolithic Silicon-Photonic DWDM PAM-4 Transceiver in 45nm CMOS SOI

📋 论文概要

本文提出一种采用45nm CMOS SOI工艺的单片集成2×5λ DWDM微环收发器，实现2×500Gb/s总速率（每通道100Gb/s PAM-4）。通过低噪声TIA、高速MRM驱动器和PWM波长锁定电路等电光协同设计，在环回测试中达到低于2.5pJ/b的能效，解决了AI/ML应用对高带宽、低功耗光互连的需求。

💡 主要创新点

• 单片集成2×5λ DWDM微环收发器，实现每通道100Gb/s PAM-4传输。
• 采用Q-tamed连续时间线性均衡器的低噪声TIA和高速MRM驱动器，提升信号质量。
• 基于PWM的可调插入损耗波长锁定电路，配合V-groove与PSR-to-CRR前端，降低耦合损耗并实现紧凑波长间隔。

🏷 关键词

📄 原文摘要

*Equally Credited Authors (ECAs) Abstract This work presents a monolithic 2×5λ DWDM microring transceiver in 45nm CMOS SOI delivering 2×500Gb/s (100Gb/s PAM-4/channel). The transceiver features a low-noise TIA with Q-tamed CTLE, a high-speed MRM driver, and a PWM-based IL-adjustable wavelength- locking circuit. V-groove and a PSR-to-CRR front end enable low coupling loss and tight λ-spacing. Through electro-photonic co-design, the transceiver achieves an efficiency <2.5pJ/b at 100Gb/s per channel in end-to-end loopback. The rapid growth of AI and machine learning (ML) is driving unprecedented bandwidth demands in hyperscale datacenters [1], necessitating short-reach, high-density optical interconnects with improved energy efficiency. Silicon photonics offers a scalable solution through monolithic integration of photonic and electronic devices, which eliminates pad and wire-bonding parasitics and enables direct fiber-to-chip coupling. Prior monolithic

👥 作者与机构

Ziang Xu*, Yalong Lin*, Jinxuan Jin*, Zhenkai Ye*, Dacheng Xu, Aolin Xu, Chaodi Sheng, Binwen Hong, Xiaojun Bi

Huazhong University of Science and Technology, Wuhan, China