An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology

📋 论文概要

本文提出一款采用7nm FinFET工艺的182mW、1-60Gb/s可配置PAM-4/NRZ收发器，针对大规模ASIC集成的功耗和面积限制进行了优化，满足了下一代数据中心交换机对高速、低功耗连接的需求。

💡 主要创新点

• 实现了1-60Gb/s宽速率范围的可配置PAM-4/NRZ收发器，适应不同数据速率需求。
• 在7nm FinFET工艺下达到182mW的低功耗，适合大规模ASIC集成（如超过500条lane的单芯片交换机）。
• 通过电路和架构创新解决了高速率下功耗与性能的权衡，支持数据中心高密度连接。

🏷 关键词

📄 原文摘要

Kumar Thasari1, Saurabh Surana1, Jun Won Jung1, Jaehun Jeong1, Heng Zhang1, Anand Vasani1, Yonghyun Shim1, Zhi Huang1, Adesh Garg1, Hsiang-bin Lee1, Bo Wu2, Feifei Liu1, Ray Wang1, Matthew Loh2, Alex Wang2, Mario Caresosa1, Bo Zhang1, Afshin Momtaz1 Broadcom, Irvine, CA Broadcom, San Jose, CA 1 2 With the COVID-19 pandemic, the faster and more reliable connectivity solutions in data centers became the critical enabler technology of our daily activities. The current 50G data center switches have more than 500 lanes within a single chip solution [1]. This massive integration puts strict restrictions on power/area consumption. Moreover, single-domain, low supply voltage operation is highly desirable for better package/board designs as well as improved silicon reliability with less aging impact. An ADC-based receiver with DSP equalization consumes higher power/area due to the time-interleaved

👥 作者与机构

Namik Kocaman1, Ullas Singh1, Bharath Raghavan1, Arvindh Iyer1,