⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一款基于ADC-DSP的112.5Gb/s PAM-4长距离收发器，采用5nm FinFET工艺，能够补偿超过50dB的信道损耗。接收机DSP包含22抽头FFE、1抽头DFE和可移动的8抽头浮动抽头FFE，有效消除反射和基线漂移。
D. Zhou1, D. Visani1, E. Hsiao1, F. Chu1, F. Lu1, G. Cui1, H. Zhang1, H. Wang1, H. Zhao1, J. Lin1, J. Gu1, L. Luo2, L. Jiang1, M. Singh1, M. Gambhir1, M. Hasan1, M. Wu1, M. J. Yoo1, P. Liu1, S. Kollu1, T. Ye2, X. Zhao2, X. Yang1, X. Han1, Y. Huang1, Y. Sun1, Z. Yu1, Z. H. Jiang1, Z. Adal1, Z. Yan1 Marvell, Santa Clara, CA Marvell, Shanghai, China 1 Referring to Fig. 6.2.2, the RX DSP data path is composed of a 22-tap FFE, a 1-tap speculative DFE and an 8-tap floating tap FFE which can be moved up to 120UI for reflection cancelling. Baseline wander correction is also implemented inside the data path. A dedicated 7-tap FFE is employed for the CDR path to achieve lower latency timing recovery and allow independent optimization of the digital equalization. After the FFE, the timing error detector (TED) is generated and a 2nd-order loop filter drives the phase interpolator inside the RX clock path. All filters are automatically adapted with LMS
Z. Guo1, A. Mostafa1, A. Elshazly 1, B. Chen1, B. Wang1, C. Han1, C. Wang1,