A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise

📋 论文概要

本文提出了一种基于环形振荡器的采样锁相环（PLL），用于高速串行链路中的低抖动多相时钟生成。该PLL在6.8-14GHz频率范围内实现了69.3fs的集成抖动，并在50mV电源噪声下保持-54.4dBc的杂散性能，解决了高频多相时钟生成中的低抖动难题。

💡 主要创新点

• 采用环形振荡器与采样技术结合，实现了超低抖动（69.3fs）的时钟生成，突破了传统环形PLL的噪声限制。
• 通过创新的电源噪声抑制技术，在50mV电源噪声下仍能保持-54.4dBc的低杂散，增强了鲁棒性。
• 实现了6.8-14GHz的宽频率范围，适用于超过100Gb/s的高速串行链路子速率时钟需求。

🏷 关键词

📄 原文摘要

Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu University of Illinois, Urbana, IL A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpassing 100Gb/s, incorporating sub-rate operations becomes essential to overcome inherent bandwidth constraints. This, in turn, demands the generation of multiple sub-rate clock phases. However, the difficulty lies in producing these clock signals with minimal jitter, particularly at high frequencies (>10GHz). Contemporary clock generators with integrated jitter below 100fsrms primarily utilize LC oscillators [1]. However, LC-based phase-locked loops (PLLs) occupy considerable space, lack efficiency in generating multiple phases, and are vulnerable to electromagnetic coupling in multi-lane SerDes systems. In contrast, ring-oscillator (RO) based architectures offer a compact footprint and inherent suitability for multi-phase

👥 作者与机构

Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia,