A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process

📋 论文概要

本文在5nm FinFET工艺中实现了一个9比特线性、14GHz的积分模式相位插值器，解决了高速SerDes中CDR对低抖动、高分辨率相位插值器的需求，提高了线性度并降低了功耗和面积。

💡 主要创新点

• 实现了9比特分辨率，高于传统7-8比特相位插值器，提升了相位调节精度。
• 采用积分模式架构在14GHz下实现高线性度，并利用5nm FinFET工艺实现低功耗紧凑设计。

🏷 关键词

📄 原文摘要

MaxLinear, Carlsbad, CA 1 2 Increased data-rates and multi-lane SerDes implementations impose stringent conditions for CDRs to produce low-jitter clocking that is capable of managing frequency and phase offsets. Consequently, high-speed phase interpolators (PIs) must be both low-power and compact for multi-lane requirements, but also high-resolution with respect to the clock period (Tperiod), with high static and dynamic phase linearity to minimize the PI jitter. Prior art in PIs is limited to 7-8b measured resolution [1-4], and INL of >500fs [1-4]. We present a 9b PI; even with the additional bits, the proposed PI consumes low power of 0.43mW/GHz and a small area. The worst rotation spur is at least 8.1dB lower (than

👥 作者与机构

Amit Kumar Mishra1, Yifei Li2, Pawan Agarwal2, Sudip Shekhar1

University of British Columbia, Vancouver, Canada