A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET

📋 论文概要

本文提出了一款基于DSP的212.5Gb/s PAM-4收发器，采用4nm FinFET工艺，针对大型AI系统互连中的高损耗信道实现了50dB的损耗补偿，解决了AI/HPC场景下芯片间数据传输的带宽瓶颈问题。

💡 主要创新点

• 实现了212.5Gb/s的超高数据率PAM-4收发，满足AI系统对极高带宽的需求。
• 通过先进DSP技术达到50dB的损耗补偿能力，突破了传统互连的距离和损耗限制。
• 采用4nm FinFET工艺，在能效和集成度上具有优势，适用于大规模AI系统互连。

🏷 关键词

📄 原文摘要

Ahmed ElShater2, Amr Khashaba2, Shih-Hao Huang1, Tsz-Bin Liu1, Atharav Atharav2, Joonyeong Lee2, Qaiser Nehal2, Mohamed Megahed2, Yusang Chun2, Cheng-En Shieh1, Vidhan Jolly2, SoonWon Kwon2, Hsin-Ta Chien1, Ke-Chung Wu1, Cheng-En Liu1, Peng Yan2, Po-Jui Li1, Chun-Han Chen1, Tzu-Shun Lin1, Pei-Chieh Liu1, Tamer Ali2 MediaTek, Hsinchu, Taiwan MediaTek, Irvine, CA 1 2 *Equally Credited Authors (ECAs) With the escalating demand of data-intensive applications such as artificial intelligence (AI) and high-performance computing (HPC), off-chip data transfer has become a critical bottleneck. Consequently, the data rate of wireline serial links has been propelled beyond 200Gb/s [1-2]. The large and complex packaging used in these links presents significant signal integrity challenges, primarily substantial channel loss and reflections. To mitigate these issues, sophisticated digital equalization techniques are required. For instance, the

👥 作者与机构

E-Hung Chen*1, Henry Park*2, Mohammed Abdullatif*2, Miguel Gandara2,