A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS

📋 论文概要

本文提出了一种8通道112Gb/s/wire单端同时双向收发器，采用动态均衡器解耦双向信号并补偿插入损耗和串扰，在28nm CMOS工艺下实现BER<10^-14和1.01pJ/b的能效，满足AI应用中die-to-die接口对高边缘密度和低误码率的需求。

💡 主要创新点

• 提出单端同时双向（SBD）架构，实现每线112Gb/s的数据速率，突破传统双向传输的带宽限制。
• 设计动态均衡器，能够同时解耦双向信号并补偿通道插入损耗和串扰，无需屏蔽层即可在3mm片上通道工作。

🏷 关键词

📄 原文摘要

*Equally Credited Authors (ECAs) 1 Abstract This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10-14, and an energy efficiency of 1.01pJ/b. The growth in artificial intelligence (AI) applications is pushing die-to-die (D2D) interfaces toward higher edge density and lower bit-error rate (BER). Increasing the per-wire data rate and reducing the data channel pitch can improve edge density, albeit at the cost of degrading signal-to-noise ratio (SNR). The degraded SNR requires better equalization to mitigate insertion loss (IL) and crosstalk to achieve a low BER. Simultaneous bi-directional (SBD) signaling and shield-less data channels are adopted in [1] for improved edge density.

👥 作者与机构

Zhiwen Huang*1, Zhifei Wang*1, Bingyi Ye2, Tianchen Ye1, Dunshan Yu1, Wei Wang1,3, Weixin Gai1,3

Peking University, Beijing, China, 2East China Normal University, Shanghai, China, 3Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China