A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS

📋 论文概要

该论文提出了一种用于小芯片（chiplet）间超短距离（XSR-MCM）通信的1.6Tb/s PAM-4收发器，单通道速率达113Gb/s。关键技术是动态接收端驱动的发送端前馈均衡器（TX-FF）自适应，通过单端曼彻斯特编码令牌式背通道实现DAC更新，提高了功耗效率并实现了更精细的抽头控制。

💡 主要创新点

• 提出动态接收端驱动的TX-FF自适应方案，利用单端曼彻斯特编码背通道从接收端调整发送端均衡，简化了系统复杂度并提升能效。
• 采用令牌式背通道通信机制，仅控制最高ON段抽头的DAC，其余ON段使用复制驱动段的Vrail电压，降低了功耗并实现更精细的均衡调节。

🏷 关键词

📄 原文摘要

M. Sorna1, M. Wielgos1, P. B. Ramakrishna2, S. Shi3, S. Parker1, U. K. Shukla2, W. Kelly1, W. Su3, Z. Yu4 Marvell, Hopewell Junction, NY Marvell, Bangalore, India 3 Marvell, Shanghai, China 4 Marvell, Santa Clara, CA better power efficiency and finer tap control only the highest ON segment of the taps are controlled by their respective programmable DACs. The other ON segments use a Vrail voltage from a replica driver segment. All the DAC updates can be dynamically adapted over a single-ended backchannel from the RX-side. The backchannel is a token-based Manchester encoded communication channel shared across the IO-core lanes. The updates are inc/dec to tap weights based on RX-driven data qualified accumulators for each tap or inc/dec to the cursor based on power envelop calculations. These updates trigger the FFE engine to enter one of the shown modes to ensure glitch-free addition/deletion of segments and DAC updates

👥 作者与机构

G. Gangasani1, D. Hanson1, D. Storaska1, H. H. Xu1, M. Kelly1, M. Shannon1,