A 112Gb/s 0.76pJ/b Reference-less Mixed-Signal PAM-4 CDR in 28nm CMOS

📋 论文概要

本文提出了一种112Gb/s的混合信号无参考PAM-4时钟数据恢复电路，采用对称线性鉴相器和bang-bang鉴频鉴相器的混合架构，结合频率捕获控制器和DCC-PEC-merged MPCG，解决了超过100Gb/s数据率下无参考PAM-4 CDR的设计难题。在28nm CMOS工艺中实现了0.76pJ/b的能效和0.11UIPP的抖动容限。

💡 主要创新点

• 提出对称线性鉴相器与bang-bang鉴频鉴相器结合的混合架构，实现快速频率捕获和低抖动恢复。
• 设计DCC-PEC-merged MPCG，将占空比校正、相位误差补偿与多相位时钟生成集成，提升时钟质量。
• 采用频率捕获控制器，无需外部参考时钟即可实现宽频率锁定范围。

🏷 关键词

📄 原文摘要

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a 112Gb/s mixed-signal reference-less PAM-4 CDR in 28nm CMOS. By proposing the hybrid architecture based on a symmetrical linear PD and a bang-bang PFD, a frequency acquisition controller and a DCC-PEC-merged MPCG, the design issues of reference-less PAM-4 CDR operating at a data rate over 100Gb/s are mitigated. The 28nm CMOS prototype achieves 0.76pJ/b efficiency and 0.11UIPP jitter tolerance at BER &10-12. With growing demand for I/O bandwidth in applications like artificial intelligence and highperformance computing, extra-short-reach over-100Gb/s energy-efficient PAM-4 serial transceivers [1-6] are increasingly popular. For the clock-and-data recovery circuits (CDR) in these transceivers, reference-less operation [7-10] is highly desirable to eliminate external crystal references for lower cost and to simplify the clock path for low-power design.

👥 作者与机构

Zhaoyu Zhang*1,2, Yiqing Xu*1,2, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, 2University of Chinese Academy of Sciences, Beijing, China