A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC

📋 论文概要

该论文提出了一款用于5G智能手机的双核深度学习加速器，采用7nm工艺，实现了3.4至13.3 TOPS/W的能效和3.6 TOPS的性能，旨在满足多种AI应用对实时性和能效的严苛要求。

💡 主要创新点

• 采用双核架构设计，通过任务并行和动态电压频率调整，在性能和功耗之间实现灵活平衡。
• 针对不同AI应用（如图像识别、去噪、语音识别）优化数据流和计算单元，提升能效比。
• 在7nm工艺下集成高带宽片上存储和专用数据通路，减少外部内存访问，降低延迟和功耗。

🏷 关键词

📄 原文摘要

Yu-Ting Kuo, Perry H Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, Shao-Yu Wang, Chin-Hua Kuo, Chih-Yu Chang, Ming-Hsien Lee, Tsung-Yao Lin, Chih-Cheng Chen MediaTek, Hsinchu, Taiwan Recent advancements in deep learning (DL) have led to the wide adoption of AI applications, such as image recognition [1], image de-noising and speech recognition, in the 5G smartphones. For a satisfactory user experience, there are stringent requirements in the real-time response of smartphone applications. In order to meet the performance expectations for DL, numerous deep learning accelerators (DLA) have been proposed for DL inference on the edge devices [25]. As depicted in Fig. 7.1.1, the major challenge in designing a DLA for smartphones is achieving the required computing efficiency, while limited by the power budget and memory bandwidth (BW). Since the overall power consumption of a smartphone system-on-a-chip (SoC) is usually constrained to 2 to 3W and

👥 作者与机构

Chien-Hung Lin, Chih-Chung Cheng, Yi-Min Tsai, Sheng-Je Hung,