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ISSCC 2020Session 22 · DRAM & HIGH-SPEED INTERFACESMemory

A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

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📋 论文概要

该论文提出了一种工作在0.8-2.3GHz的正交误差校正器,采用最小总延迟跟踪技术,可校正高达101.6ps的相位误差,解决了多相时钟因器件失配引起的相位误差导致数据采样窗口缩小的问题。

💡 主要创新点

核心指标
0.8-2.3GHz频率范围,可校正误差范围101.6ps
重要性
发表年份
ISSCC 2020

🏷 关键词

正交误差校正多相时钟最小延迟跟踪DRAM接口

📄 原文摘要

paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade the valid data sampling window. To reduce phase error, several multiphase correction schemes have been proposed [1-4]. The active poly-phase filter-based open-loop scheme exhibits a small RMS jitter contribution, but the remaining phase error after the error correction is considerably varied and large in its operating frequency range

👥 作者与机构

Soyeong Shin1, Han-Gon Ko1, Sungchun Jang2, Dongkyun Kim2, Deog-Kyoon Jeong1

Seoul National University, Seoul, Korea SK hynix, Icheon, Korea 1 2 As data transfer rates increase, clock frequencies used for high-speed data

分类:Memory · 年份:ISSCC 2020