⚡ 本页包含 AI 生成的分析内容,仅供参考
该论文提出了一种工作在0.8-2.3GHz的正交误差校正器,采用最小总延迟跟踪技术,可校正高达101.6ps的相位误差,解决了多相时钟因器件失配引起的相位误差导致数据采样窗口缩小的问题。
paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade the valid data sampling window. To reduce phase error, several multiphase correction schemes have been proposed [1-4]. The active poly-phase filter-based open-loop scheme exhibits a small RMS jitter contribution, but the remaining phase error after the error correction is considerably varied and large in its operating frequency range
Soyeong Shin1, Han-Gon Ko1, Sungchun Jang2, Dongkyun Kim2, Deog-Kyoon Jeong1
Seoul National University, Seoul, Korea SK hynix, Icheon, Korea 1 2 As data transfer rates increase, clock frequencies used for high-speed data