A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS

📋 论文概要

该论文提出了一款在12nm工艺下实现的可编程卷积高效神经处理单元芯片，峰值性能达到825TOPS，旨在解决数据中心中卷积神经网络的高效计算需求。通过优化卷积运算的硬件架构和可编程性，实现了高吞吐量和能效比。

💡 主要创新点

• 针对卷积神经网络计算特点，设计了高效卷积加速架构，提升了运算效率。
• 采用12nm先进工艺实现高集成度，实现825TOPS的峰值性能。
• 具备可编程性，支持多种网络模型，具有灵活的配置能力。

🏷 关键词

📄 原文摘要

Yun Li1, Long Chen1, Zhen Chen1, Lu Liu3, Zhuyu He3, Yu Yan3, Jun He3, Jun Mao3, Xiaotao Zai3, Xuejun Wu3, Yongquan Zhou3, Mingqiu Gu1, Guocai Zhu1, Rong Zhong1, Wenyuan Lee1, Ping Chen1, Yiping Chen1, Weiliang Li3, Deyu Xiao3, Qing Yan3, Mingyuan Zhuang3, Jiejun Chen3, Yun Tian3, Yingzi Lin3, Wei Wu3, Hao Li4, Zesheng Dou4 Alibaba, Sunnyvale, CA, 2Alibaba, Seattle, WA Alibaba, Shanghai, China, 4Alibaba, Hangzhou, China 1 3 Convolutional neural networks (CNN) represent a key application in data centers, which calls for accelerators that are: 1) efficient for CNN computations; 2) having high throughput to be cost-efficient; and, 3) with adequate programming flexibility for algorithm upgrades. Lacking of the availability of such a chip in the market, we designed our own. Matrix multiplication (MM) and convolution (CONV) are the top-2 deep learning (DL) operations requiring intensive computation. Most

👥 作者与机构

Yang Jiao1, Liang Han1, Rong Jin2, Yi-Jung Su1, Chiente Ho1, Li Yin3,