A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

📋 论文概要

该论文提出了一种4路交织、10GS/s采样率、8位分辨率的时域ADC。通过16倍插值级间增益技术，在18GHz输入频率下实现了>37.5dB的SNDR，解决了高速ADC的大输入电容和带宽限制问题。

💡 主要创新点

• 提出4路交织与16倍插值结合的时域ADC架构，有效提升转换速率和带宽。
• 采用插值级间增益技术，在不增加额外功耗的情况下改善ADC的线性度和高频性能。
• 通过小输入电容设计，避免了高速ADC对大功耗输入缓冲器的依赖。

🏷 关键词

📄 原文摘要

University of Lisboa, Lisbon, Portugal 1 2 The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR ADCs with a large interleaving factor suffer from a large input capacitance [1] and often have a limited BW, or otherwise they necessitate a power-hungry broadband input buffer [2]. Flash ADCs [3] not only face the same challenge from the large input parasitics but also limited resolutions resulting from offset. Recently, time-domain ADCs [4-5] have shown promising speeds resulting from a small input capacitance due to their inherent voltage-to-time converter (VTC) as a sub-channel wideband buffer, but also show limited resolution (6b) due to the mismatches between the time steps. When targeting a higher resolution [6], calibration is necessary to unify the time quantization steps and often requires a known input

👥 作者与机构

Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, Rui P. Martins1,2

University of Macau, Macau, China