An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique

📋 论文概要

该论文提出了一种基于8nm工艺的18Gb/s/pin GDDR6物理层（PHY）设计，通过发射机带宽扩展和接收机训练技术解决了高速信令中的读写校准问题，满足了自动驾驶和人工智能等应用对高数据吞吐量的需求。

💡 主要创新点

• 提出发射机带宽扩展技术，提升高速信号传输质量。
• 提出接收机训练技术，优化读写校准过程，提高数据可靠性。

🏷 关键词

📄 原文摘要

Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyoung-Hoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park Samsung Electronics, Hwaseong, Korea Recent emerging applications, such as autonomous vehicles, artificial intelligence, and deep learning, require a large amount of data computation. The GDDR6 interface is a candidate solution because it can operate up to 64GB/s (16Gb/s/pin × 32 pins) with a lower cost than HBM. To communicate with GDDR6 DRAM [1,2] the GDDR6 PHY requires high-speed signaling and, more importantly, read/write calibration for optimal margins. In this work, to transmit 18Gb/s data, while meeting the required GDDR6 I/O 1.35V supply, a thin-oxide high-voltage output driver [3] is used with a high-speed level shifter. A dual-mode equalizer is developed in the transmitter to selectively compensate for intersymbol interference (ISI) and far-end crosstalk (FEXT). For an accurate

👥 作者与机构

Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim,