A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

📋 论文概要

该论文提出了一种基于积分型DAC的FMCW锁相环，用于快速锯齿波调频连续波雷达，解决了传统PLL带宽限制导致的线性度问题，实现了10GHz载波、1.2GHz带宽和23MHz/μs斜率下的90kHz rms频率误差，功耗仅12mW。

💡 主要创新点

• 采用积分型DAC替代传统电荷泵，实现高线性度快速调频，克服PLL带宽限制。
• 通过两点调制方案，在低功耗下实现大带宽、高斜率FMCW信号合成。

🏷 关键词

📄 原文摘要

continuous-wave (FMCW) radars are a viable solution for high-resolution indoor localization and tracking applications. The fast saw-tooth FMCW chirp needs to be synthesized with a short ramp time, large chirp bandwidth (CBW), and high linearity for accurate detection of targets. FractionalN phase-locked loop (PLL) can be used to synthesize the chirp. The two-point-modulation (TPM) scheme implemented in [1-3] overcomes the problem of the PLL bandwidth limitation during a fast saw-tooth chirp modulation. To be integrated on a smart device, the power consumption of the radar sensor needs to be reduced. A digital-to-time-converter (DTC)-based sub-sampling PLL (SSPLL) [1] can be used for a high-linearity chirp generation, which eliminates

👥 作者与机构

Pratap Tumkur Renukaswamy1,2, Nereo Markulic1, Sehoon Park1,2,

Anirudh Kankuppe1,2, Qixian Shi 1, Piet Wambacq1,2, Jan Craninckx1 imec, Leuven, Belgium;2Vrije Universiteit Brussel, Brussels, Belgium 1 Frequency-modulated