A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

📋 论文概要

该论文提出了一种基于7nm FinFET CMOS工艺的计算存储融合（CIM）SRAM宏单元，用于机器学习应用。它解决了传统CIM方案中面积、噪声容限和权值精度的权衡问题，实现了高能效和高吞吐量。

💡 主要创新点

• 采用新型SRAM位单元设计，在保持小面积的同时提高了并行度和噪声容限。
• 利用7nm FinFET工艺优化能效和性能，实现了351TOPS/W的能效和372.4GOPS的吞吐量。
• 有效减少了离片权重访问，降低了能耗和延迟，适用于AI边缘设备。

🏷 关键词

📄 原文摘要

computations and reduces off-chip weight access to reduce energy consumption and latency, specifically for AI edge devices. Prior CIM approaches demonstrated tradeoffs for area, noise margin, process variation and weight precision. 6T SRAM [1-3] provides the smallest cell area for CIM, but cell stability limits the number of activated cells, resulting in low parallelization. 10T and twin-8T [4-5] isolate the read/write paths for noise margin improvement, however both require special design of the bit cell using logic layout rules, resulting in over a 2× area overhead compared to foundry yield-optimized 6T SRAMs. Furthermore, single-bit precision of weights, in prior work [1-4], cannot meet the requirement for high-precision operations and scalability for large neural networks.

👥 作者与机构

Qing Dong1, Mahmut E. Sinangil1, Burak Erbagci1, Dar Sun2,

Win-San Khwa2, Hung-Jen Liao2, Yih Wang2, Jonathan Chang2 TSMC, San Jose, CA TSMC, Hsinchu, Taiwan 1 2 Compute-in-memory (CIM) parallelizes multiply-and-average (MAV)