Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for HighPerformance Processors with Wide Voltage-Frequency Operating Range

📋 论文概要

该论文提出了一种可重构瞬态电流模式全局互连电路，在10nm CMOS工艺中实现，用于高性能处理器。它解决了高电压下RC互连延迟不随逻辑门延迟按比例改善的问题，提高了互连吞吐量和能效。

💡 主要创新点

• 提出可重构瞬态电流模式电路，动态调整驱动能力以适应不同工作模式。
• 采用电流模式信号传输，降低RC延迟影响，提升全局互连速度。
• 在10nm CMOS工艺中实现，兼顾高性能与低功耗。

🏷 关键词

📄 原文摘要

Raghavan Kumar, H. Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR The clock frequency of high-performance processors in the high-voltage turbo/burst operation mode [1] is governed primarily by the RC-dominated global interconnects in the communication fabrics and NoCs, since the interconnect RC delay does not improve proportionally with logic gate delay at higher voltages. Prior current-mode and pre-emphasis techniques for improved interconnect throughput and energy efficiency [2-5] do not address the critical turbo/burst mode latency requirements, and do not consider tunability across a wide voltagefrequency operating range in high-performance processors. Their transmit/receive circuits with complicated data recovery and differential signaling incur major latency and wiring resource overheads, especially for shorter bus distances typical

👥 作者与机构

Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen,