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本文提出了一种基于环形放大器的低压差稳压器（LDO），通过副本电路增强电源抑制比（PSR），解决了数字LDO输出纹波大、PSR差以及依赖时钟频率的问题。该LDO在0.4-1.2V输入电压范围内实现了0.0057mm²的芯片面积和55fs的瞬态FoM。
Digital low-dropout regulators (DLDOs) are commonly used in low-power systemon-chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate. However, the digital control of the power gate results in an output voltage ripple and a decrease in the powersupply rejection (PSR). In addition, the transient performance of DLDOs depends strongly on the operating clock frequency. Several techniques such as eventdriven operation [1], VCO-embedded time-based control [2], and computed regulation [3] have been proposed to reduce the dependency on the operating clock frequency. Nonetheless, the output voltage ripple and PSR degradation of DLDOs still need to be addressed. Although an inverter-based analog LDO [4] that provides a low-voltage operation and a wide-band PSR has been proposed, as compared to DLDOs it has a slow transient response and narrow input voltage
Jun-Eun Park, Jeongho Hwang, Jonghyun Oh, Deog-Kyoon Jeong
Seoul National University, Seoul, Korea