A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS

📋 论文概要

本文提出了一种基于模拟时间-数字转换器（ATDC）的4单元空间信号处理器，实现了500MHz调制带宽、6位分辨率、1GS/s采样率，功耗仅40mW，采用65nm工艺。该设计解决了传统移相器阵列在大带宽密集干扰网络中的挑战，实现了高能效的真时延空间信号处理。

💡 主要创新点

• 采用模拟时间-数字转换器（ATDC）替代传统移相器，实现宽带真时延空间信号处理，降低复杂度和功耗。
• 在65nm工艺下实现了4单元紧凑型处理器，支持500MHz调制带宽和1GS/s采样，功耗仅40mW，能效比显著优于同类方案。
• 通过将时间域信号处理与数字化结合，实现了频率无关的阵列增益，适用于下一代密集干扰环境下的相控阵系统。

🏷 关键词

📄 原文摘要

Next-generation phased-array systems with large modulated bandwidths (BW) and high energy efficiency will enable Gb/s wireless communications. The spatial signal processing at this large scale using state-of-the-art phase-shifter (PS)based arrays causes unsolved challenges in dense interference-limited networks with large modulated BWs. In addition, the need for frequency-independent array gain demands low-complexity and energy/area-efficient true-time-delay(TTD)based spatial signal processing. Recent works have demonstrated beam-nulling [1,2] and beamforming [2-4] for PS and TTD systems. In [1], a baseband(BB)to-RF impedance translation is used for beam nulling with a swept single tone only. In [2], an autonomous spatial filter without external controls is implemented for large modulated BW. However, its PS-based method introduces frequencydependent filtering for applications at lower RF carrier frequencies (large fractional

👥 作者与机构

Erfan Ghaderi, Chase Puglisi, Shrestha Bansal, Subhanshu Gupta

Washington State University, Pullman, WA