A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking

📋 论文概要

该论文提出了一种12.8-15.2GHz分数-N数字Bang-Bang锁相环，采用数字频率误差恢复技术实现快速锁定，同时达到66fsrms的超低抖动，满足5G毫米波频段对本地振荡器低于90fsrms的抖动要求。相比模拟PLL，该设计在功耗和面积上更具优势。

💡 主要创新点

• 提出数字频率误差恢复机制，在锁定过程中快速纠正频率误差，显著缩短锁定时间，同时保持低抖动性能。
• 采用Bang-Bang鉴相器与数字环路滤波器，避免了模拟PLL中面积大的无源滤波器，实现了小面积和低功耗。
• 在12.8-15.2GHz频率范围内实现了66fsrms的积分抖动，优于5G标准的要求。

🏷 关键词

📄 原文摘要

substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for millimeter-wave frequency bands [1]. To satisfy such stringent requirements, while at the same time guaranteeing fast lock, analog PLLs have been preferred over digital implementations in recent literature [1,2]. Digital bang-bang PLLs, on the other hand, consume less power and occupy smaller footprint due to the absence of analog loop filters. Digital bang-bang PLLs, however, generally suffer from poor locking performance, which is due to the bang-bang phase detector (BBPD) overloading in presence of large frequency errors, and from increased jitter due

👥 作者与机构

Alessio Santiccioli1, Mario Mercandelli1, Luca Bertulessi1, Angelo Parisi1,

Dmytro Cherniak2, Andrea Leonardo Lacaita1, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy, 2Infineon Technologies, Villach, Austria 1 The