A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS

📋 论文概要

提出一种在22nm FinFET工艺中实现的自校准分数-N MDLL，工作频率为1.2-3.8GHz，核心面积仅0.0052mm²。通过2位时间周期比较器实现自校准，并采用DTC增益校正环路补偿误差，结合三态反相器多路选择器和开关电容阵列实现粗调和细调延迟。

💡 主要创新点

• 首次采用2位时间周期比较器实现全合成MDLL的自校准，无需传统数字校准电路
• 将自定义三态反相器多路选择器和开关电容阵列作为宏单元集成到数字自动布局布线流程中，实现紧凑面积
• 通过DTC增益校正环路补偿延迟级误差，提高分数-N频率合成精度

🏷 关键词

📄 原文摘要

Intel, Hillsboro, OR errors, which are compensated by the DTC-gain-correction loop. Each delay stage uses tristate inverter-based multiplexer (MUX) and switched capacitor banks to realize coarse and fine delays, respectively. These blocks are custom designed and used as macro cells in digital place-and-route (P&R) flow. The reference injection point that determines the coarse DTC delay is set by making one of the MUX selections (Sel0-4) logic high. For example, assuming Sel0=1 as the zero or minimum delay state, when Sel3 becomes 1, the reference edge goes through two more tristate MUX stages, which introduces 0.2T path delay. Similarly, Sel1=1 corresponds to 0.4T delay, and so on. The output of 2nd and 4th stages of the coarse DTC drives a 7b phase interpolator (PI) based the fine DTC to generate delay steps of 0.2T/27. Sel0-4 and the PI weight (W) are generated from an external 32b frequency control word (FCW) that determines the frequency multiplication factor.

👥 作者与机构

Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent Carlton