⚡ 本页包含 AI 生成的分析内容,仅供参考
本文提出一款128Gb、1b/cell、96字线层的3D闪存芯片,通过优化读取和编程电路,将随机读取延迟降低至4µs,编程时间缩短至75µs,旨在满足存储级内存(SCM)对低延迟和高性能的需求。
Sanad Bushnaq1, Takuyo Kodama1, Yuki Ishizaki1, Yoko Deguchi1, Akio Sugahara1, Akihiro Imamoto1, Norichika Asaoka1, Ryosuke Isomura1, Takaya Handa1, Junichi Sato2, Hiromitsu Komai1, Atsushi Okuyama1, Naoaki Kanagawa1, Yasufumi Kajiyama1, Yuri Terada1, Hidekazu Ohnishi1, Hiroki Yabe3, Cynthia Hsu3, Mami Kakoi1, Masahiro Yoshihara1 KIOXIA, Yokohama, Japan, 2KIOXIA Systems, Yokohama, Japan Western Digital, Milpitas, CA 1 3 In recent years, storage class memory (SCM) has attracted attentions and various R&D results have been reported as it has great potential to improve computingsystem performance by filling the latency gap between fast main memories (DRAM) and slow storage (flash memories and hard-drives). SCM’s lower cost than DRAMs enables main-memory space in a system to expand dramatically [1]; its faster access time, in comparison to flash memories such as a solid state drive (SSD), can allow it to boost the performance of the main storage system. With
Toshiyuki Kouchi1, Noriyasu Kumazaki1, Masashi Yamaoka1,