EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation

📋 论文概要

该论文在65nm CMOS工艺中实现了一个AES-256加密引擎，通过电流域签名衰减技术（超过350倍）有效抑制了与密钥相关的电磁和功耗泄漏，显著提高了对侧信道攻击的抵御能力。

💡 主要创新点

• 提出了一种基于电流域签名衰减的物理层防护方法，同时抑制电磁和功耗泄漏。
• 实现了超过350倍的电流域签名衰减，显著提升AES-256的侧信道攻击抗性。
• 在65nm CMOS中完成了芯片实现与验证，证明了该技术的实用性和有效性。

🏷 关键词

📄 原文摘要

Shovan Maity1, Baibhab Chatterjee1, Donghyun Seo1, Muya Chang2, Avinash Varna3, Harish Krishnamurthy4, Sanu Mathew4, Santosh Ghosh4, Arijit Raychowdhury2, Shreyas Sen1 Purdue University, West Lafayette, IN Georgia Institute of Technology, Atlanta, GA, 3Intel, Chandler, AZ 4 Intel Labs, Portland, OR 1 2 Computationally-secure cryptographic algorithms when implemented on physical platforms leak critical physical signals correlated with the secret key in the form of power consumption and electromagnetic (EM) emanations. This can be exploited by an adversary, leading to side-channel attacks (SCA) that can recover the secret key. Circuit-level on-chip countermeasures include a switched-capacitor current equalizer [1], charge-recovery logic [2], an integrated voltage regulator (IVR) [3], and an all-digital low-dropout (LDO) regulator [4], which suffer from performance degradation, high power/area overheads because of large embedded

👥 作者与机构

Debayan Das1, Josef Danial1, Anupam Golder2, Nirmoy Modak1,