技术领域

Hardware Security

36 篇相关论文 (2008–2026)

ISSCC 2026 Session 25 Hardware Security
A PVT Variation- and Attack-Tolerant Metastability-Based TRNG Using Binary Search in 2nm
Yelim Youn1, Yong Lim1,2, Jongmi Lee1, Dongyeon Hong1, Wan Kim1, Yong-Sik Kwak1, Kyoung-Jun Moon1, Bogyeong Kang1, Sangm
Abstract This work presents a single source, metastability-based TRNG using binary search with offset-tunable comparator. The proposed TRNG operates without warm-up time and is robust against low-frequency noise, PVT var
Samsung Electronics, Hwaseong, Korea, 2now with Yonsei University, Seo
ISSCC 2026 Session 25 Hardware Security
A Sub-Threshold All-NMOS Reconfigurable PUF with Secure Configuration Selection for Stable 6b/Cell
Shufan Xu*, Kunyang Liu*, Lando Chan, Hironori Tagawa, Hirofumi Shinohara, Kiichi Niitsu
*Equally Credited Authors (ECAs) Abstract In this work, a reconfigurable PUF featuring secure configuration selection is presented. Without exposing secret PUF data, it achieves 6 stable bits per cell (b/cell) and “zero”
Kyoto University, Kyoto, Japan
ISSCC 2026 Session 25 Hardware Security
TinyPAD: A 166µm2/lane Variation-Tolerant Probing-Attack Detector for an 8Gb/s/lane Chip-to-Chip Interface in 16nm FinFET
Mao Li1, Rentao Wan1, Sanu K Mathew2, Vivek De2, Mingoo Seok1
Abstract We present TinyPAD, a 166µm2/lane probing-attack detector in 16nm FinFET with 82pF maximum supported loading as well as 0.2pF minimum detectable capacitance (MDC) that operates robustly over -40 to125°C and from
Columbia University, New York, NY, 2Intel, Hillsboro, OR
ISSCC 2026 Session 25 Hardware Security
A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking
Cankun Zhao1,2, Hanyue Shui1,2, Bohan Yang1,2, Wenping Zhu1,2, Yuluan Cao1,2, Zhang Hou1,2, Yuqi Liu1,2, Xiangdong Han1,
Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, China Wuxi Research Institute of Applied Technologies, Tsinghua University, Beijing, China, 4Micro Innovation Integrated Circuit Desi
Hanning Wang1,2, Jinjiang Yang3, Min Zhu4, Aoyang Zhang1,2, Leibo Liu1
ISSCC 2026 Session 25 Hardware Security
A 0.05mm2 1.19-to-7.34mW SQIsign-1D Isogeny-Based Post-Quantum Signature Verification Accelerator for IoT
Krishna Sai Tarun Ramapragada, Utsav Banerjee
Abstract This work presents a 0.05mm2 and 1.19-to-7.34mW hardware accelerator for the isogenybased NIST post-quantum digital signature candidate SQIsign. Our Montgomery multiplier design enables 2× speedup and energy sav
Indian Institute of Science, Bengaluru, India
ISSCC 2026 Session 25 Hardware Security
OmniCrypt: A 435.86M-GOPS/W Bootstrappable Multi-Scheme FHE Accelerator with On-Chip Data Generation for Privacy-Preserving Computation
Adiwena Putra*, Hyunjun Cho*, Sungwoong Yune, Cuong Manh Duong, Jaeho Jeon, Joo-Young Kim
*Equally Credited Authors (ECAs) Abstract OmniCrypt is a silicon-proven multi-scheme FHE accelerator that supports both bootstrapping and scheme switching. Fabricated in 28nm CMOS (12.96mm2), it integrates three speciali
KAIST, Daejeon, Korea
ISSCC 2026 Session 25 Hardware Security
A 16nm 0.042mm2 0.66µJ/Ops Lightweight MLWE PQC KEM with Cryptanalysis-ASIC Co-Optimization
Archisman Ghosh*1, Ming-Che Li*1, Lingke Ding1, Suparna Kundu2, Abdullah Sayeed1, Angshuman Karmakar3, Harshit Naman1, S
(ECAs) 1 Abstract Resource-limited devices demand post-quantum cryptography (PQC) within stringent power, area, and memory limits. To our knowledge this work introduces the first cryptanalysis-ASIC co-optimized PQC IC, a
Ingrid Verbauwhede2, Shreyas Sen1 Purdue University, West Lafayette, I
ISSCC 2026 Session 25 Hardware Security
A 28nm 0.48mJ/boot Torus FHE Processor for Arbitrary Computation on Encrypted Data
Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Song Wang, Zhen Yang, Jun Han
Abstract This work presents a 3.24mm2 torus fully homomorphic encryption (FHE) processor fabricated in 28nm CMOS, featuring: 1) a security-preserving low-bit-width torus quantization with keys hints reducing latency by 6
Fudan University, Shanghai, China
ISSCC 2026 Session 25 Hardware Security
A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks
Kai Cheng1, Yunbo Huang1, Zunsong Yang1, Li Wang1, Hongyu Ren1, Xiaoyu Shan1, Pui-In Mak2, Yong Chen3, Bo Li1
Abstract In Paper 25.10 a floating-latch-based true random number generator (FL-TRNG) is presented that achieves an energy efficiency of 0.066pJ/b by leveraging a floating reservoir capacitor as its power supply. This ar
Institute of Microelectronics of the Chinese Academy of Sciences, Beij
ISSCC 2026 Session 25 Hardware Security
HERACLES: 8192-Way SIMD Programmable Scalable Fully-Homomorphic Encryption SoC for Privacy-Preserving Cloud Computing in Intel 3 CMOS
Anupam Golder1, Raghavan Kumar1, Sachin Taneja1, Kylan Race2, Paolo Aseron1, James Greensky1, Wen Wang1, Huijing Gong1,
Vikram Suresh1, Adish Vartak1, AppaRao Challagundla2, Jeremy Casas1, Poornima Lalwaney1, Duhyeong Kim1, Christopher N. Gutierrez1, Ernesto Zamora Ramos1, Wonhee Cho1, Jose M. Rojas Chaves1, Michael Steiner1, Dan Lake1, N
ISSCC 2025 Session 17 Hardware Security
A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process
Nandish Mehta1, Stephen Tell2, Sanquan Song1, Sudhir Kudva1, Brian Zimmer1,
Mahmut Sinangil1, C. Thomas Gray2 Nvidia, Santa Clara, CA Nvidia, Durham, NC 1 2 On-chip oscillators are emerging as a critical circuit for improving the security of systemon-chips (SoCs). Many SoCs utilize an on-chip os
ISSCC 2025 Session 17 Hardware Security
An Eye-Opening Arbiter PUF for Fingerprint Generation Using Auto-Error Detection for PVT-Robust Masking and Bit Stabilization Achieving a BER of 2e-8 in 28nm CMOS
Bjoern Driemeyer, Holger Mandry, David-Peter Wiens, Joachim Becker,
John G. Kauffman, Maurits Ortmanns University of Ulm, Ulm, Germany Physically Unclonable Functions (PUFs) enable hardware identification and security key generation without storing them in non-volatile memory or exposing
ISSCC 2025 Session 17 Hardware Security
An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies and implemented in the 3nm (GAA) and 8nm (FinFet) technology nodes. The evaluations were performed on the test dies of both technologies across various process corners and operational conditions, where each die contains six PUF macros.
Bohdan Karpinskyy, Yong Ki Lee, Sumin Noh, Yunhyeok Choi, Jieun Park,
Figure 17.4.3 presents the distribution of &Vth in PUF cells, as measured in the analog Monte Jisu Kang, Taewook Park, Eunhye Oh, Gapkyung Kim, Sungha Lee, Hyunwoo Ko, Carlo simulation of 3nm (GAA) PUF cells, along with
ISSCC 2025 Session 17 Hardware Security
A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation
Liang-Hsin Lin, Yao-Kai Yang, Chia-Hsiang Yang
Secure data processing has become critical to privacy-preserving in the data-driven AI era. Multi-party computation (MPC) enables computations among multiple parties (users) in a collaborative way while preserving data p
National Taiwan University, Taipei, Taiwan
ISSCC 2025 Session 17 Hardware Security
A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing
Sijia Lu1,2, Wenping Zhu1,2, Bohan Yang1,2, Jiajun Yang1,2, Tongwei Dai1,2,
Chen Chen1,2, Xiangdong Han1,2, Jinjiang Yang3,$Hanning Wang1,2, Min Zhu4, Shaojun Wei1,2, Aoyang Zhang1, Leibo$Liu1,2 Tsinghua University, Beijing, China Beijing National Research Center for lnformation Science and Tech
ISSCC 2025 Session 17 Hardware Security
Sensor-Less Laser Voltage-Probing Attack Detection via Run-Time-Leakage-Shift Monitoring with 4.35% Area Overhead
Hui Zhang*1, Longyang Lin*2, Dingyi Xiong1, Massimo Bruno Alioto1
Southern University of Science and Technology, Shenzhen, China 1 2 *Equally Credited Authors (ECAs) Higher levels of security are constantly demanded in view of the ever-expanding threats of physical attacks [1–7], whose
National University of Singapore, Singapore, Singapore
ISSCC 2023 Session 15 Hardware Security
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS
Raghavan Kumar1, Avinash Varna2, Carlos Tokunaga1, Sachin Taneja1,
from cryptographic engines to extract secret keys. A single fault injected into the penultimate AES round using directed laser pulses or voltage/clock glitches corrupts 4 output bytes (Fig. 15.5.1), reducing key search s
Vivek De1, Sanu Mathew1 Intel, Hillsboro, OR Intel, Chandler, AZ 1 2 F
ISSCC 2023 Session 15 Hardware Security
A 28nm 68MOPS 0.18µJ/Op Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing
Guiming Shi1, Zhanhong Tan1, Dapeng Cao2, Jingwei Cai1, Wuke Zhang3,
of tremendous emerging information applications, providing various reliable and high-performance services based on vast amounts of individual and organizational data. Paillier homomorphic encryption (PHE)
Yifu Wu3, Kaisheng Ma1 Tsinghua University, Beijing, China Xi’an JiaoT
ISSCC 2023 Session 15 Hardware Security
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor
Achieving 10Gbps/W Network Routing, 40ms CAN Bus, Start-Up and 1.4mW Standby Power
in the Control domain can start the CAN service in parallel with booting for other (nonCAN) services. Moreover, decryption by a secure CPU and data loading from external memory can be performed in parallel by double buff
ISSCC 2023 Session 15 Hardware Security
A 2.19µW Self-Powered SoC with Integrated Multimodal
Energy Harvesting, Dual-Channel up to -92dBm WRX and, Energy-Aware Subsystem
Everactive, Charlottesville, VA, 2Everactive, Santa Clara, CA, 3Everactive, Ann Arbor, MI preserved. The SoC is designed to operate near-threshold to achieve its low power floor. Thus, an AVFS block is included to improv
ISSCC 2023 Session 15 Hardware Security
A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber
Xinjian Liu1, Daniel S. Truesdell1, Omar Faruqe1, Lalitha Parameswaran2,
Michael Rickley2, Andrew Kopanski2, Lauren Cantley2, Austin Coon2, Matthew Bernasconi2, Tairan Wang2, Benton H. Calhoun1 University of Virginia, Charlottesville, VA MIT Lincoln Laboratory, Lexington, MA 1 2 Rapid reducti
ISSCC 2022 Session 34 Hardware Security
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/DualCore/Blind-Bulk AES Engine in Intel 4 CMOS
Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu,
Amit Agarwal, Vivek K. De, Sanu K. Mathew Intel, Hillsboro, OR Power and electromagnetic (EM) side-channel attacks (SCA) exploit data-dependent power consumption from cryptographic engines to extract embedded secret keys
ISSCC 2022 Session 34 Hardware Security
A Threshold-Implementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks
Saurav Maji1, Utsav Banerjee2, Samuel H. Fuller1,3, Anantha P. Chandrakasan1
Indian Institute of Science, Bengaluru, India 3 Analog Devices, Wilmington, MA 1 2 Neural network (NN) hardware accelerators are being widely deployed on low-power IoT nodes for energy-efficient decision making. Embedded
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2022 Session 34 Hardware Security
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems
Yihong Zhu1, Wenping Zhu1, Min Zhu2, Chongyang Li1, Chenchen Deng1,
era, post-quantum cryptography (PQC) processors are required to ensure quantum-secure communication and e-commerce with high throughput, while maintaining adequate flexibility to execute different crypto-primitives, such
Chen Chen1, Shuying Yin1, Shouyi Yin1, Shaojun Wei1, Leibo Liu1 Tsingh
ISSCC 2021 Session 36 Hardware Security
An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3×10-8 Bit Error Rate
Yan He*, Dai Li*, Zhanghao Yu, Kaiyuan Yang
*Equally Credited Authors (ECAs) Physically unclonable functions (PUF) have emerged as a promising solution for secure and low-cost key storage and hardware authentication. A key challenge in PUF designs is ensuring the
Rice University, Houston, TX
ISSCC 2021 Session 36 Hardware Security
A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology
Jaehan Park, Jae-Yoon Sim
Physically unclonable functions (PUFs) have been actively investigated as a promising solution for low-cost secure authentication in Internet of Things (IoT) applications. A PUF should generate unique challenge-response
Pohang University of Science and Technology, Pohang, Korea
ISSCC 2021 Session 36 Hardware Security
A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In
Kunyang Liu, Zihan Fu, Gen Li, Hongliang Pu, Zhibo Guan, Xingyu Wang,
lowenergy and low-latency authentication requirements of IoT applications, owing to their exponential number of challenge-response pairs (CRPs). However, Strong PUFs suffer from vulnerability to modeling attacks and a hi
Xinpeng Chen, Hirofumi Shinohara Waseda University, Kitakyushu, Japan
ISSCC 2021 Session 36 Hardware Security
An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control
Archisman Ghosh1, Debayan Das1, Josef Danial1, Vivek De2, Santosh Ghosh2, Shreyas Sen1
side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical sidechannel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include current equali
Purdue University, West Lafayette, IN Intel, Hillsboro, OR 1 2 Mathema
ISSCC 2021 Session 36 Hardware Security
Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security including PUF responses lying at bin boundaries (affecting masking only marginally, see BER below).
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
In Fig. 36.1.4, the TRNG was confirmed to have consistent measured output quality across very different data patterns (all 0’s for minimum jitter vs. random data), 0.8-to-1V supply and -10 to 75°C temperature. The min-en
ISSCC 2020 Session 27 Hardware Security
Physically Unclonable Function in 28nm FDSOI Technology Achieving High Reliability for AEC-Q100 Grade 1 and ISO26262 ASIL-B
Yunhyeok Choi, Bohdan Karpinskyy, Kyoung-Moon Ahn, Yongsoo Kim,
Physically Unclonable Functions (PUFs) are considered a secure method for security key generation because they generate responses that exist only during operation. A challenge regarding the use of PUFs is to achieve high
Soonkwan Kwon, Jieun Park, Yongki Lee, Mijung Noh Samsung Electronics,
ISSCC 2020 Session 27 Hardware Security
EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation
Debayan Das1, Josef Danial1, Anupam Golder2, Nirmoy Modak1,
Shovan Maity1, Baibhab Chatterjee1, Donghyun Seo1, Muya Chang2, Avinash Varna3, Harish Krishnamurthy4, Sanu Mathew4, Santosh Ghosh4, Arijit Raychowdhury2, Shreyas Sen1 Purdue University, West Lafayette, IN Georgia Instit
ISSCC 2020 Session 27 Hardware Security
M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power
Pranay Prabhat1, Benoît Labbe1, Graham Knight1, Anand Savanth1,
Jonas Svedas1, Matthew J Walker1, Supreet Jeloka2, Philex Ming-Yan Fan1, Fernando García-Redondo1, Thanusree Achuthan1, James Myers1 ARM, Cambridge, United Kingdom, 2ARM, Austin, TX 1 Recent research has shown subthresho
ISSCC 2020 Session 27 Hardware Security
A 65nm Energy-Harvesting ULP SoC with 256kB CortexM0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System
Jonathan K. Brown1, David Abdallah2, Jim Boley3, Nicholas Collins1,
Kyle Craig2, Greg Glennon2, Kuo-Ken Huang3, Christopher J. Lukas2, William Moore3, Richard K. Sawyer2, Yousef Shakhsheer2,4, Farah B. Yahya2, Alice Wang3, Nathan E. Roberts2, David D. Wentzloff1, Benton H. Calhoun2 Evera
ISSCC 2019 Session 25 Hardware Security
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator
Arvind Singh1, Monodeep Kar2, Sanu Mathew2, Anand Rajan2, Vivek De2, Saibal Mukhopadhyay1
information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or swit
Georgia Institute of Technology, Atlanta, GA Intel, Hillsboro, OR 1 2
ISSCC 2019 Session 25 Hardware Security
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source with <6×10-6 Native Bit Error Rate
Yachuan Pang1, Bin Gao1, Dong Wu1, Shengyu Yi1, Qi Liu1,
Wei-Hao Chen2, Ting-Wei Chang2, Wei-En Lin2, Xiaoyu Sun3, Shimeng Yu3, He Qian1, Meng-Fan Chang2, Huaqiang Wu1 Tsinghua University, Beijing, China National Tsing Hua University, Hsinchu, Taiwan 3 Georgia Institute of Tec
ISSCC 2019 Session 25 Hardware Security
A 562F2 Physically Unclonable Function with a Zero-Overhead Stabilization Scheme
Dai Li, Kaiyuan Yang
Internet of Things (IoT) devices bring a growing demand for secure, low-power, and low-cost secret key and ID storage solutions. Physically unclonable functions (PUFs) are one of the most promising alternatives to conven
Rice University, Houston, TX