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本文提出首款密码分析-ASIC协同优化的后量子密码芯片，在Intel16工艺上实现了极小的面积、功耗和内存占用。相比最先进的M-LWE加速器面积减少8倍，相比通用PQC处理器面积减少509倍，能量-面积积降低8.5倍，适用于资源受限的物联网设备。
(ECAs) 1 Abstract Resource-limited devices demand post-quantum cryptography (PQC) within stringent power, area, and memory limits. To our knowledge this work introduces the first cryptanalysis-ASIC co-optimized PQC IC, achieving minimal area, power, and memory footprint. This approach achieves an area reduction of 8× relative to the state-of-the-art M-LWE accelerator and up to 509× compared to a generic PQC processor. Fabricated in Intel16, this IC operates over a frequency range of 0.1MHz to 1.03GHz and achieves an 8.5× reduction in energy-area product. Resource-limited devices such as IoT edge devices, medical implants, wearables, etc., are increasingly intertwined with sensitive personal data, ranging from audio and video streams
Archisman Ghosh*1, Ming-Che Li*1, Lingke Ding1, Suparna Kundu2, Abdullah Sayeed1, Angshuman Karmakar3, Harshit Naman1, Sarthak Antal1,
Ingrid Verbauwhede2, Shreyas Sen1 Purdue University, West Lafayette, IN, 2KU Leuven ESAT, Leuven, Belgium, 3Indian Institute of Technology, Kanpur, India *Equally Credited Authors