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本文提出一款面积0.05mm²、功耗1.19-7.34mW的SQIsign后量子签名验证硬件加速器，针对IoT应用。通过优化的Montgomery乘法器实现2倍加速与节能，高效内存组织节省31%面积，性能较汇编优化软件提升一个数量级。
Abstract This work presents a 0.05mm2 and 1.19-to-7.34mW hardware accelerator for the isogenybased NIST post-quantum digital signature candidate SQIsign. Our Montgomery multiplier design enables 2× speedup and energy savings, and efficient memory organization provides 31% area savings. We demonstrate SQIsign-1D uncompressed signature verification in a small form factor for IoT applications with order of magnitude improvement in performance and energy-efficiency compared to assembly-optimized software. Rapid advances in quantum computing technologies have motivated the theoretical construction and practical implementation of post-quantum cryptography (PQC) [1]. After several years of rigorous analysis, NIST has recently announced its first set of PQC standards [2]. The primary recommendations for digital signatures are Dilithium (ML-DSA) and Falcon (FN-DSA) [3]. Both are lattice-based schemes known for their strong security
Krishna Sai Tarun Ramapragada, Utsav Banerjee
Indian Institute of Science, Bengaluru, India