An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies and implemented in the 3nm (GAA) and 8nm (FinFet) technology nodes. The evaluations were performed on the test dies of both technologies across various process corners and operational conditions, where each die contains six PUF macros.

📋 论文概要

本文提出了一种仅使用标准单元实现的物理不可克隆函数（PUF）设计，通过利用工艺失配中的阈值电压倾斜（Vth-Tilting）提取熵。该设计在3nm GAA和8nm FinFET两种先进工艺节点上实现并验证了其有效性。

💡 主要创新点

• 首次在3nm GAA和8nm FinFET先进工艺中实现基于标准单元的PUF，利用Vth倾斜产生随机性
• 无需定制电路或模拟模块，完全基于数字标准单元，提高了设计的可移植性和低成本
• 通过阈值电压倾斜效应增强工艺失配的差异性，提升PUF的唯一性和可靠性

🏷 关键词

📄 原文摘要

Figure 17.4.3 presents the distribution of &Vth in PUF cells, as measured in the analog Monte Jisu Kang, Taewook Park, Eunhye Oh, Gapkyung Kim, Sungha Lee, Hyunwoo Ko, Carlo simulation of 3nm (GAA) PUF cells, along with its mathematical behavior. The &Vth Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin behavior follows a Gaussian distribution due to random and distinct process mismatches Samsung Electronics, Hwaseong, Korea This paper presents a physically unclonable function (PUF) design implemented solely with standard cells. The proposed PUF extracts entropy from process mismatches in the threshold voltages (Vth) of inverting cells. An additional Vth tilting scheme supports efficient PUF enrollment by screening potentially unstable responses, requiring processing only at nominal voltage/temperature (V/T) conditions. The PUF design has been implemented in 3nm GAA and 8nm FinFet technology nodes and verified on test chips across various

👥 作者与机构

Bohdan Karpinskyy, Yong Ki Lee, Sumin Noh, Yunhyeok Choi, Jieun Park,