An 8.3-to-18Gbps Reconfigurable SCA-Resistant/DualCore/Blind-Bulk AES Engine in Intel 4 CMOS

📋 论文概要

该论文提出了一种在Intel 4 CMOS工艺上实现的8.3-18Gbps可重构AES引擎，通过双核架构和盲体偏置技术抵抗侧信道攻击，解决了传统防护方法无法抵御强大攻击者的问题。

💡 主要创新点

• 提出可重构的侧信道攻击抵抗架构，结合双核和盲体偏置技术，实现灵活的安全防护。
• 在Intel 4先进工艺上实现高速AES引擎，支持8.3-18Gbps的吞吐率。
• 通过加法掩码等数学方法提供可证明安全性的侧信道泄漏抑制。

🏷 关键词

📄 原文摘要

Amit Agarwal, Vivek K. De, Sanu K. Mathew Intel, Hillsboro, OR Power and electromagnetic (EM) side-channel attacks (SCA) exploit data-dependent power consumption from cryptographic engines to extract embedded secret keys. While series-connected voltage regulators [1,2] and arithmetic countermeasures like heterogenous Galois-field arithmetic [3] provide acceptable levels of side-channel leakage suppression, they cannot defend against determined adversaries. Random additive masking [4] on the other hand, provides a provably-secure solution [5] that disrupts first-order correlations between measured power/EM signatures and secret keys, while incurring 2× overhead in area and power consumption. In this paper, we demonstrate a reconfigurable AES accelerator fabricated in Intel 4 CMOS process with minimum-timeto-disclosure (MTD) > 1B power/EM traces in on-demand SCA-resistant mode, while providing a 2.2× boost in encryption performance during a dual-core mode of operation

👥 作者与机构

Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu,