A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking

📋 论文概要

本文提出了一种低开销的SHA-3引擎，通过融合双轨预充电逻辑和非对称掩码技术，实现了对毛刺和跳变鲁棒的安全防护。该引擎在0.046mm²面积下，仅增加17%面积开销和27%能量开销，且无延迟损失，同时通过了超过1亿次功率/电磁TVLA测试。

💡 主要创新点

• 提出了一种无毛刺的双轨预充电逻辑（Glitch-free DPL），将掩码状态减少3倍，显著降低了寄存器面积和逻辑能耗。
• 采用非对称掩码共享刷新机制（LMDPL），在保持安全性的同时进一步优化了面积和能量效率。
• 实现了0%延迟开销的硬件安全设计，同时达到可证明的毛刺和跳变鲁棒安全等级。

🏷 关键词

📄 原文摘要

Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, China Wuxi Research Institute of Applied Technologies, Tsinghua University, Beijing, China, 4Micro Innovation Integrated Circuit Design, Wuxi, China 1 3 Abstract This 0.046mm2 SHA-3 engine demonstrates overheads of only 17% area, 27% energy, and 0% latency while achieving provable glitch- and transition-robust security (power/EM TVLA MTD>100M). Glitch-free DPL reduces masked states by 3×, resulting in a 72,950μm2 register area reduction and lower logic energy. LMDPL refresh preserves secure asymmetric-share mapping. Masked transitions enable partial replacement of DPL with SRL, saving 50,852μm2 in registers, precharge gates, and multiplexers. Cryptographic hash functions are fundamental components in modern security systems.

👥 作者与机构

Cankun Zhao1,2, Hanyue Shui1,2, Bohan Yang1,2, Wenping Zhu1,2, Yuluan Cao1,2, Zhang Hou1,2, Yuqi Liu1,2, Xiangdong Han1,2, Shuying Yin1,2, Weinan Chen1,2,

Hanning Wang1,2, Jinjiang Yang3, Min Zhu4, Aoyang Zhang1,2, Leibo Liu1,2 School of Integrated Circuits, Tsinghua University, Beijing, China, 2State Key