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本文提出了一种面向高速内存接口的32Gb/s数字密集型单端PAM-4收发器，通过采用2抽头基于时间的均衡技术，解决了传统NRZ链路在高信道损耗下受码间干扰限制的问题，实现了更高的带宽效率。
Single-ended transceivers that can deliver high-data rates at reduced supply voltages are required to meet the ever-growing demands of future memory interfaces. The performance of conventional non-return-to-zero (NRZ) links is usually limited by inter-symbol-interference (ISI) noise caused by high channel losses. Alternative schemes such as duobinary [1], three or four level pulse amplitude modulation (PAM-3, PAM-4) [2], and multi-band signaling [3] were proposed to increase bandwidth efficiency. In particular, PAM-4 signaling utilizes four signal levels to send 2b per unit interval, at the expense of complex TX and RX circuits resulting in higher power consumption and larger chip area. While this approach has been gaining popularity for ultra-high speed (>50Gb/s) links, a more compact implementation is needed for memory interface applications. In this paper, we propose a digital-intensive PAM-4 receiver targeted at memory
Po-Wei Chiu, Chris Kim
University of Minnesota, Minneapolis, MN