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AMD提出基于chiplet的第二代Infinity Fabric SoC，采用三种不同工艺的chiplet实现异构集成，用于服务器和客户端产品。该架构在7nm工艺上实现高性能、高性价比和高能效，并保持向后兼容和可扩展性。
AMD, Austin, TX 1 2 AMD’s “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targeting server and client markets, respectively (Fig. 2.2.1). The chiplet architecture enables leading edge 7nm [1] CPUs for multiple markets, while retaining backward compatibility to complex IO and memory subsystems in a scalable design with high reuse for improved time-to-market. A key benefit is the heterogeneous technology deployed between the CPUs and the IO/mixed-signal IP. It is well known that shrink factors in advanced nodes are much lower for analog circuitry than for digital logic and SRAM. By keeping the memory interfaces and SerDes in mature 12nm technology, costs are mitigated since those circuits see a very small shrink factor to 7nm and very little performance or power gain from advanced nodes. A lowcost 12nm IO die (IOD) with the high-yielding 8 “Zen2” co
Samuel Naffziger1, Kevin Lepak2, Milam Paraschou1, Mahesh Subramony2
AMD, Fort Collins, CO