A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

📋 论文概要

该论文提出了一种12.5GHz分数-N类型-I采样PLL，通过采用采样技术实现了58fs的集成抖动，解决了传统模拟PLL中大型模拟滤波器难以在纳米级CMOS工艺中缩放的问题，同时避免了数字PLL中时间数字转换器的量化噪声。

💡 主要创新点

• 提出了一种类型-I采样PLL架构，利用采样技术实现低抖动和分数-N频率合成。
• 通过优化环路设计和噪声抑制技术，在12.5GHz输出频率下实现了58fs的集成抖动，满足5G毫米波收发器对低抖动时钟的需求。

🏷 关键词

📄 原文摘要

oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier frequencies. Analog PLLs demonstrated to have successfully met the required performance levels with integer-N [1] and fractional-N frequency synthesis [2], while involving large analog filters that are not amenable to down scaling in nanoscale CMOS processes. By contrast, digital PLLs are compact and scalable, but suffer from quantization noise of time-to-digital converters (TDCs), which adds up to thermal noise [3]. A viable solution to achieve both compactness and very low jitter is to employ an analog type-I PLL with a sampling phase detector (SPD) [4].

👥 作者与机构

Mario Mercandelli1, Alessio Santiccioli1, Angelo Parisi1, Luca Bertulessi1,

Dmytro Cherniak2, Andrea Leonardo Lacaita1, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy 2 Infineon Technologies, Villach, Austria 1 Local