A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

📋 论文概要

本文提出了一款12位18GS/s的射频采样ADC，集成了宽带跟踪保持放大器和后台校准技术，解决了高速时间交织ADC中因子ADC数量增加导致的带宽降低、失配杂散和功耗增大的问题。

💡 主要创新点

• 集成宽带跟踪保持放大器，支持18GS/s的直接射频采样，减少输入电容并提高带宽。
• 采用后台校准技术，校正时间交织ADC的采样时刻和带宽失配，降低交织杂散。

🏷 关键词

📄 原文摘要

consumption enable direct RF sampling, more integration, flexibility and lower cost for communication, instrumentation and other applications. The state of the art of interleaved RF converters enables up to 10GS/s with 12-14b of resolution [1-4]. However, to increase the sample rate, the number of interleaved sub-ADCs tends to increase, which degrades the interleaving spurs due to sampling time and bandwidth mismatch, increases the input capacitance, reduces the input bandwidth, and increases the power consumption of the ADC. Randomization of the interleaved sub-ADCs helps alleviate the impact of the interleaving spurs, but that degrades the noise and increases power consumption in a manner that gets progressively worse as the input frequency and number of interleaved sub-ADCs

👥 作者与机构

Ahmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Scott Bardsley,

Chris Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett Analog Devices, Greensboro, NC High sample rate ADCs with high input bandwidth and low power