A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS

📋 论文概要

该论文提出了一种基于单相位域电平交叉和嵌入技术的噪声整形非均匀采样ADC，旨在解决传统连续时间ΔΣ调制器在高带宽需求下所需高采样率、高线性度及环路延迟补偿的挑战。通过非均匀采样和噪声整形技术，实现了40MHz带宽、76.2dB SNDR和78.0dB DR的卓越性能。

💡 主要创新点

• 采用单相位域电平交叉方法实现非均匀采样，避免传统多比较器或复杂时钟方案，降低功耗和复杂度。
• 结合噪声整形技术与嵌入技术（如嵌入式量化器或反馈），在不增加过多过采样率的情况下提升有效分辨率和动态范围。
• 非均匀采样架构有效放宽了对模拟构建块速度和线性度的要求，同时简化了过量环路延迟补偿设计。

🏷 关键词

📄 原文摘要

A low-power, wide-bandwidth, and high-dynamic-range (DR) ADC is one of the critical building blocks in a wireless receiver design, in which a continuous-time delta-sigma modulator (CT DSM) has become a popular choice. However, the demand for a wider bandwidth has increased the sampling rate, Fs, which requires high-speed and highly linear analog building blocks, and excess loop delay compensation (ELDC) [1]. Reducing the over-sampling ratio can relax these requirements, but it results in more quantization levels and high-order noise shaping (NS). The feedback DAC often becomes a design challenge, as its distortion degrades ADC performance and can require linearization and higher supply voltage [2-4]. To avoid these issues, this work proposes a voltagecontrolled oscillator (VCO)-based noise-shaping nonuniform sampling (NUS) ADC architecture, including an NUS modulator and a nonuniform digital signal

👥 作者与机构

Tzu-Fan Wu, Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA