A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

📋 论文概要

该论文提出了一种基于CMOS-RRAM的神经形态核心，通过动态可重构数据流和原位可转置权重，实现了灵活的数据流和权重访问模式，解决了传统存算一体设计在支持概率图模型和循环神经网络等复杂模型时的灵活性不足问题。

💡 主要创新点

• 提出动态可重构数据流架构，支持多种神经网络模型的数据流模式。
• 实现原位可转置权重，无需额外存储即可灵活切换权重矩阵的转置访问。
• 基于CMOS-RRAM混合工艺，实现高能效的存算一体计算。

🏷 关键词

📄 原文摘要

Yan Liao3, Dabin Wu3, Stephen Deiss2, Bin Gao3, Priyanka Raina1, Siddharth Joshi4, Huaqiang Wu3, Gert Cauwenberghs2, H.-S. Philip Wong1 Stanford University, Stanford, CA, 2University of California, San Diego, CA, Tsinghua University, Beijing, China, 4University of Notre Dame, Notre Dame, IN 1 3 Many powerful neural network (NN) models such as probabilistic graphical models (PGMs) and recurrent neural networks (RNNs) require flexibility in dataflow and weight access patterns as shown in Fig. 33.1.1 Typically, ComputeIn-Memory (CIM) designs do not implement such dataflows or do so by replicating circuits at the memory periphery such as ADCs/neurons along both the rows and columns of the memory array, leading to an overhead in operation. This paper describes a CIM architecture implemented in a 130nm CMOS/RRAM process, that delivers the highest reported computational energy-efficiency of 74 tera-multiply-accumulates per second per watt (TMACS/W) for RRAM-based CIM

👥 作者与机构

Weier Wan1, Rajkumar Kubendran2, S. Burc Eryilmaz1, Wenqiang Zhang3,