A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators

📋 论文概要

该论文提出了一种计算自适应的弹性时钟链技术，用于2D处理元件阵列加速器。通过动态调整时钟链长度，利用计算过程中的时序裕量，提升性能或能效，解决了传统固定时钟周期浪费时序裕量的问题。

💡 主要创新点

• 提出弹性时钟链结构，可根据计算负载自适应调整时钟周期，灵活利用时序裕量。
• 实现动态时序增强，在运行中实时检测并调整时钟链，提升加速器频率或降低电压。
• 专门针对2D PE阵列加速器优化，适用于机器学习等数据密集型应用，提高能效比。

🏷 关键词

📄 原文摘要

Dynamic timing error detection and correction techniques, e.g. razor flops, have been previously applied to microprocessors to exploit the dynamic timing margin within pipelines [1]. Adaptive clock techniques have also been adopted to enhance microprocessor performance, such as schemes to reduce the timing guardband for on-chip supply droops [2-3] or to exploit instruction-level dynamic timing slack [4]. Recently, 2D PE array-based accelerators have been developed for machine learning (ML) applications. Many efforts have been dedicated to improve the energy efficiency of such accelerators, e.g. DVFS management for the DNN under various bit precision [5]. A razor technique was also applied to a 1D 8-MAC pipelined accelerator to explore timing error tolerance [6]. Despite the above efforts, a fine-grained dynamic-timing-based technique has not been implemented within a large 2D array based ML accelerator. One main challenge comes from

👥 作者与机构

Tianyu Jia, Yuhao Ju, Jie Gu

Northwestern University, Evanston, IL