A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM

📋 论文概要

该论文提出了一种21.7-26.5GHz的电荷共享锁定正交PLL，通过隐式数字频率跟踪环路实现低抖动。解决了传统亚采样PLL和注入锁定PLL在毫米波频段功耗高、面积大的问题。

💡 主要创新点

• 采用电荷共享锁定技术替代传统亚采样或注入锁定，降低功耗和面积。
• 引入隐式数字频率跟踪环路，无需额外模拟环路滤波器，实现75fs超低抖动。

🏷 关键词

📄 原文摘要

Ireland 1 2 Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1,2] due to their ability to achieve ultra-low jitter (<100fs). However, as indicated in Fig. 17.6.1(top-left), sub-sampling PLLs (SS-PLL) typically suffer from highpower consumption, especially in mmW VCO buffers, which isolate the VCO from its sampler for reducing reference spurs, and in the high-speed dividers [2-4]. Also, the analog loop filter usually occupies large area. On the other hand, the IL technique for mmW frequency generation requires power-hungry high-frequency injection (~GHz) to fully suppress the oscillator phase noise [1,4] and cannot ensure robustness over PVT (process, voltage, temperature) [4], which requires

👥 作者与机构

Yizhe Hu1, Xi Chen1, Teerachot Siriburanon1, Jianglin Du1, Zhong Gao1,

Vivek Govindaraj1, Anding Zhu1, Robert Bogdan Staszewski1,2 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin,