A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo

📋 论文概要

本文提出了一款128Gb容量、8层堆叠、带宽512GB/s的HBM2E DRAM，通过伪四分之一存储体结构、功率分散技术和基于指令的在线PMBI解决了高带宽内存的功耗和测试挑战。

💡 主要创新点

• 采用伪四分之一存储体结构，优化了存储体访问模式，降低了功耗并提高了带宽利用率。
• 引入功率分散技术，通过动态分配功率资源，减少了峰值功耗并提升了能效。
• 提出基于指令的在线PMBI（并行内存内置自测）方法，实现了高速率下的原位测试，提高了测试效率和可靠性。

🏷 关键词

📄 原文摘要

Dong Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Woo Young Lee, Tae Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park, Seokwoo Choi, Young Jun Park, Chang Kwon Lee, Chunseok Jeong, Jae-seung Lee, Sang Hun Lee, Woo Sung We, Jong Chan Yun, Doobock Lee, Junghyun Shin, Seungchan Kim, Junghwan Lee, Jiho Choi, Yucheon Ju, Myeong-Jae Park, Kang Seol Lee, Youngdo Hur, Daeyong Shim, Sangkwon Lee, Junhyun Chun, Kyo-Won Jin SK hynix, Icheon, Korea There is enormous demand for high-bandwidth DRAM: in application such as HPC, graphics, high-end server and artificial intelligence. HBM DRAM was developed [1] using the advances in package technology: TSV, microbump and silicon-interposer. Owing to these advances, HBM has a much higher bandwidth, at a lower pin speed rate, than conventional DRAM. However, the 3D-stack

👥 作者与机构

Quarter Bank Structure, Power Dispersion and an, Instruction-Based At-Speed PMBIST