A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation

📋 论文概要

本文提出了一种单通道3.3GS/s、6位全动态流水线ADC，通过后放大残差生成技术实现了低功耗（5.5mW）和高速转换，解决了传统闪存ADC在高分辨率下面积和能效低下的问题。采用全动态电路避免了静态功耗，适用于ADC-based串行链路和5G接收机。

💡 主要创新点

• 提出全动态流水线架构，消除了静态偏置电流，显著降低功耗。
• 采用后放大残差生成技术，在不增加额外比较器的情况下提升转换速度。
• 通过优化残差放大时序，实现3.3GS/s采样率下仅5.5mW功耗。

🏷 关键词

📄 原文摘要

Chi-Hang Chan1, Jan Craninckx2, Rui P. Martins1,3 University of Macau, Macau, China imec, Leuven, Belgium 3 University of Lisboa, Lisbon, Portugal 1 2 Multi-GS/s ADCs are key blocks for ADC-based serial links and mm-wave 5G receivers. The fastest architecture is the flash ADC [1], but the exponentially growing complexity with resolution makes it energy and area inefficient. Interpolation techniques [2] can reduce the number of comparators but result in lower conversion speeds, while an aggressive interpolation factor in [3] also increases the calibration complexity. SAR ADCs are by far the most power efficient, but only with time interleaving can they reach the required speeds. Hence, pipelined architectures are the preferred choice, but also here clock speeds above 1GS/s are not readily achieved, and the power consumption of the residue amplifier is critical. Previous work [5] explores the option of the fully dynamic

👥 作者与机构

Zihao Zheng1,2, Lai Wei1,2, Jorge Lagos2, Ewout Martens2, Yan Zhu1,